Through Silicon Interposer Wafer for MEMS Packaging
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Solution Overview
Problem
Current wafer level packaging techniques for MEMS devices, such as CMOS-MEMS and dummy cap-MEMS bonding, face limitations in flexibility and functionality due to size matching requirements and material constraints, while through silicon interposer (TSI) bonding offers flexibility but is costly and prone to degassing issues that degrade the vacuum environment.
Innovation Solution
A through silicon interposer wafer with filled silicon vias and cavities that provide support and electrical feedthrough, using conductive materials separated by dielectric layers, and incorporating getter materials to maintain vacuum integrity, reducing the number of masking steps and fabrication costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If through silicon interposer (TSI) bonding is used for MEMS packaging, then flexibility and adaptability are improved, but manufacturing cost and process complexity increase
Solution Approach 1:
The TSI wafer is divided into distinct functional regions including cavity portions for MEMS encapsulation, through silicon vias for electrical connections, and support structures. This segmentation allows each region to be optimized independently while simplifying the overall manufacturing process by reducing the need for complex multi-step patterning.
Solution Approach 2:
The TSI wafer structure serves multiple functions simultaneously: it provides mechanical support for the MEMS device, creates hermetic encapsulation cavities, establishes electrical connections through filled vias, and offers thermal management pathways. This multi-functionality reduces the need for separate components and processing steps.
2Adaptability or versatility
If through silicon interposer (TSI) bonding is used for MEMS packaging, then flexibility and adaptability are improved, but manufacturing cost increases
Solution Approach 1:
Multiple fabrication steps are merged into fewer processing operations. The cavity formation, via creation, and support structure integration are accomplished in an integrated sequence rather than as separate masking and patterning steps, directly reducing manufacturing complexity and cost.
Solution Approach 2:
Support structures and through silicon vias are formed and positioned in advance during TSI wafer fabrication, before MEMS device assembly. This preliminary action simplifies subsequent packaging steps and reduces the overall number of processing stages required.
3Reliability
If conventional TSI fabrication with PECVD dielectrics is used, then encapsulation is achieved, but degassing occurs that degrades vacuum environment
Solution Approach 1:
The patent changes the material parameter from conventional PECVD dielectrics to low-outgassing materials such as silicon oxide or silicon nitride deposited through atomic layer deposition (ALD). This parameter change maintains encapsulation integrity while significantly reducing degassing that would otherwise degrade the vacuum environment for MEMS operation.
Data Source
AI summary
A through silicon interposer wafer and method of manufacturing the same. A through silicon interposer wafer having at least one cavity formed therein for MEMS applications and a method of manufacturing the same are provided. The through silicon interposer wafer includes one or more filled silicon vias formed sufficiently proximate to the at least one cavity to provide support for walls of the at least one cavity during subsequent processing of the interposer wafer.