Time Slot Interchange Switch Bit Error Rate Testing
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Solution Overview
Problem
Time slot interchange switches lack effective bit error rate testing capabilities, which is crucial for ensuring data integrity in telecommunications systems, particularly in environments with varying data rates and complex channel switching requirements.
Innovation Solution
A time slot interchange switch is designed with a serial-to-parallel converter, data memory, connection memory, memory controller, bit error rate receiver, and transmitter, enabling bit error rate testing by converting serial data to parallel, storing, reading, and calculating bit error rates, and generating pseudo-random number sequences for testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bit error rate testing capabilities are added to time slot interchange switches, then data integrity is improved, but device complexity increases
Solution Approach 1:
The patent combines the bit error rate testing function with the existing time slot interchange switch architecture by integrating a BERT receiver and transmitter within the switch fabric. The testing channels are merged with the data channels, allowing the switch to perform both switching and error rate testing functions using the same hardware resources, thereby improving data integrity without proportionally increasing overall device complexity.
Solution Approach 2:
The time slot interchange switch is designed to serve multiple functions: it performs time slot interchange switching for data channels while simultaneously providing bit error rate testing capabilities. The same switch fabric and memory structures are utilized for both data switching and test pattern switching, making the device universal and multi-functional, which addresses the contradiction by achieving improved reliability without linearly increasing complexity.
2Measurement precision
If multiple testing channels are supported, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent divides the testing functionality into separate testing channels that can be independently configured and monitored. Each channel can have its own BERT receiver for precise measurement, allowing multiple simultaneous measurements with high precision. The switch fabric segments the testing paths, enabling independent control and measurement of each channel's bit error rate without requiring a completely separate testing infrastructure for each channel.
Solution Approach 2:
The time slot interchange switch itself acts as an intermediary that facilitates multiple bit error rate testing channels. Rather than requiring separate external testing equipment for each channel, the switch provides the intermediary function of routing test patterns and receiving test results for multiple channels through its internal fabric and memory structures, thereby improving measurement precision across multiple channels without proportionally increasing external testing infrastructure complexity.
Data Source
AI summary
In accordance with the invention, time slot interchange switches (“TSIS”) with bit error rate testing are described. The bit error rate testing includes creating a channel of data appropriate for bit error rate testing and monitoring the bit error rate testing on that channel.