Time-Sensitive Networking Controller with Local Look-Up Tables

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Solution Overview

Problem

Current networking devices face latency and determinism issues due to reliance on central processor units for memory address look-ups, which hinders efficient data retrieval and transmission in time-sensitive applications.

Innovation Solution

Implementing an enhanced gate control list with local look-up tables and multiple queues within the network interface controller, allowing for direct memory access and scheduling based on predetermined times, reducing CPU load and enhancing determinism and throughput.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If the networking device uses a central processor unit for memory address look-ups, then the device can maintain simplicity in structure, but the end-to-end latency increases and determinism deteriorates

Engineering Contradiction:
Improvestructure simplicityVSAvoidend-to-end latency
Core Design Contradiction:
Device complexityVSLoss of time

Solution Approach 1:

The patent extracts the memory address look-up function from the central processor unit and places it in a local look-up table within the networking device. This separation allows the networking device to perform look-ups independently without CPU intervention, reducing latency while maintaining structural simplicity through modular design.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent implements preliminary action by pre-loading memory addresses and control information into the local look-up table before data transmission is needed. This allows the networking device to quickly retrieve pre-computed addresses during time-critical operations, eliminating the need for real-time CPU processing and reducing end-to-end latency.

Inventive Principle:
Principle #10Preliminary action

2Device complexity

If the networking device uses a central processor unit for data retrieval, then the device structure remains simple, but the CPU efficiency decreases due to increased load

Engineering Contradiction:
Improvedevice structureVSAvoidCPU efficiency
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent extracts data retrieval operations from the central processor unit and implements them locally within the networking device using a local look-up table. This offloads CPU-intensive operations from the processor, improving CPU efficiency while maintaining simple device structure through distributed functionality.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The networking device performs self-service by autonomously retrieving data using the local look-up table without requiring CPU intervention. The device independently completes data retrieval operations, reducing the CPU workload and improving overall system productivity while keeping the device structure simple.

Inventive Principle:
Principle #25Self-service

3Device complexity

If the networking device uses centralized control for packet transmission, then the control logic remains simple, but the determinism deteriorates due to CPU scheduling variability

Engineering Contradiction:
Improvecontrol logicVSAvoiddeterminism
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent extracts time-critical control functions from centralized CPU control and implements them locally within the networking device. The local look-up table stores pre-computed control information that enables deterministic packet transmission without CPU scheduling variability, while the overall control logic remains simple through decentralized execution.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent applies preliminary action by pre-computing and storing transmission control information in the local look-up table before packets need to be transmitted. This allows the networking device to execute predetermined control actions with high determinism, eliminating the variability introduced by real-time CPU scheduling while maintaining simple control logic.

Inventive Principle:
Principle #10Preliminary action

4Device complexity

If the networking device performs real-time address look-ups through the CPU, then the system maintains centralized control, but the throughput decreases due to processing bottlenecks

Engineering Contradiction:
Improvecontrol architectureVSAvoiddata throughput
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent extracts address look-up operations from the centralized CPU control architecture and implements them locally within the networking device. This distributes the processing load, eliminates CPU bottlenecks, and increases data throughput while maintaining centralized control architecture through coordinated operation between CPU and local look-up tables.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent implements preliminary action by pre-computing and caching address information in the local look-up table before data transmission occurs. This allows the networking device to perform rapid address retrieval without real-time CPU intervention, increasing throughput by removing processing bottlenecks while preserving centralized control architecture.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11620255B2Time sensitive networking device
Publication Date: 2023.04.04 INTEL CORP
  • US11620255B2 patent drawing
  • US11620255B2 patent drawing
  • US11620255B2 patent drawing

AI summary

The present disclosure generally relates to a device, method, or system for time sensitive networking. In an example, the device can include a time-sensitive networking controller and a scheduler. The device also includes an enhanced gate control list maintained on the time-sensitive networking controller to include a direct memory access address, a launch time, and a pre-fetch time for a data packet. The device may also include a transmitter of the time-sensitive networking controller to transmit the data packet retrieved using the direct memory access address at the launch time identified by the scheduler.