TSN Gate Control Circuitry Bypassing Cycle Timer
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Solution Overview
Problem
Gate overrun events in Time-Sensitive Networking (TSN) applications cause issues with time synchronization between systems due to incomplete frame transmission before the next gate operation window, leading to latency and synchronization problems.
Innovation Solution
A method and circuit arrangement that configures gate states based on a current gate control list, using a cycle timer to initiate gating cycles and a list configuration circuit to bypass the cycle timer for direct signaling, ensuring zero delay between expected and actual gate operations, and employing a pre-fetch circuit to execute next operations without waiting for previous ones to complete, thus reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the cycle timer circuit is used to signal the start of a gating cycle, then the gate operations are synchronized with the timing signal, but latency is introduced between the expected and actual gate operations
Solution Approach 1:
The list configuration circuit prepares and establishes the new gate control list in advance before the gating cycle begins. When the list is ready, it directly signals the list execution circuit to start execution immediately, eliminating the waiting period that would otherwise occur with the cycle timer circuit. This preliminary preparation of the gate control list resolves the contradiction by ensuring both timing synchronization and minimal latency.
2Stability of the object's composition
If the list configuration circuit waits for the cycle timer signal to start a new gate control list, then the gating cycle timing is maintained, but gate overrun events occur when frame transmission is not completed before the next gate operation window
Solution Approach 1:
The list configuration circuit establishes the new gate control list in advance and directly signals the list execution circuit to begin execution immediately upon completion of list establishment. This preliminary action ensures that gate operations start without delay, allowing frame transmission to complete before the next gate operation window, thereby preventing gate overrun events while maintaining gating cycle timing stability.
Solution Approach 2:
The system monitors the completion status of frame transmission and uses this feedback to determine when to establish a new gate control list. The list configuration circuit receives feedback about transmission completion and adjusts the timing of list establishment accordingly, ensuring that new gate operations are initiated only when previous transmissions are complete, thus preventing gate overrun while maintaining stable gating cycle timing.
3Adaptability or versatility
If multiple gate control lists are active at different times to accommodate different network traffic patterns, then network traffic scheduling flexibility is improved, but the complexity of managing and switching between lists increases
Solution Approach 1:
The list configuration circuit serves multiple functions: it receives new gate control lists, establishes them as current lists, and directly signals the list execution circuit to start execution. This multi-functional design simplifies the overall system by consolidating list management operations into a single circuit, reducing the complexity of managing multiple gate control lists while maintaining the flexibility to accommodate different network traffic patterns.
Data Source
AI summary
A time-sensitive networking system includes gate control circuits configured to control egress of data from multiple queues, respectively. A list execution circuit configures gate states of the plurality of gate control circuits based on a current gate control list that specifies a sequence of operations. Each operation specifies the gate states of the gate control circuits. A cycle timer circuit transmits a timing signal that signals to start a gating cycle by the list execution circuit. A list configuration circuit inputs a new gate control list and establishes the new gate control list as the current gate control list. The list configuration circuit transmits an initial cycle start signal directly to the list execution circuit, bypassing the cycle timer circuit, in response to completion of establishing the new gate control list as the current gate control list.