Time-Sensitive Networking Gate Control via Individual Queue Lists
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Solution Overview
Problem
Existing time-aware shapers in Time-Sensitive Networking (TSN) face challenges in efficiently handling complex gate-open and gate-close events, leading to long common gate control lists and increased computational effort, especially when dealing with unfavorable repetition periods and overlapping events, which is difficult to implement effectively in hardware.
Innovation Solution
The use of individual queue gate lists, each with a sequence of entries specifying gate states and accumulated durations, simplifies gate control and reduces the number of entries required, allowing for easier calculation of open times and improved hardware implementation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a common gate control list is used to control multiple gates, then all gates can be managed within a single unified structure, but the list becomes very long and requires significant computational effort to calculate the next gate-close event time
Solution Approach 1:
The patent divides the common gate control list into separate individual gate control lists, one for each gate. Each list contains only the events relevant to that specific gate, segmenting the large unified structure into smaller manageable units. This reduces the computational burden when calculating next gate-close event times, as each gate controller only needs to process its own list rather than searching through a long common list.
Solution Approach 2:
The patent introduces a new dimension to gate control by organizing events in individual lists per gate rather than a single common list. This dimensional change allows each gate controller to independently manage its own event sequence, transforming the problem from a centralized computational task into distributed, parallel processing across multiple gate controllers.
2Productivity
If individual queue gate lists are used for each gate, then the number of entries is reduced and calculation is simplified, but additional memory structures are required
Solution Approach 1:
The patent segments the gate control data into individual lists stored in memory, one for each gate. While this creates multiple separate memory structures, each structure is smaller and more efficient than a single large list. The segmentation allows parallel access and reduces the memory access time required for gate control operations.
Solution Approach 2:
The patent pre-organizes gate events into individual lists during system initialization or configuration, before runtime operation. This preliminary action of structuring the data into separate lists eliminates the need for complex runtime calculations and sorting, allowing gate controllers to simply follow the pre-arranged sequences during operation.
3Adaptability or versatility
If software-based control is used to accommodate complex cycles, then flexibility is improved, but hardware implementation becomes more difficult and expensive
Solution Approach 1:
The patent segments the complex gate control function into independent, identical gate controller units, each handling one gate. This segmentation allows the same hardware design to be replicated multiple times to handle different gates with different patterns, providing flexibility through replication rather than through complex centralized control logic.
Solution Approach 2:
The patent makes the gate control system dynamic by allowing each individual gate controller to operate independently with its own event list. This enables the system to adapt to different gate patterns and repetition periods through configuration of the individual lists rather than requiring complex runtime decision-making logic in hardware.
Data Source
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AI summary
A network device (1) comprising a set of queues (2) and a time-aware shaper (3) which comprises a set of transmission gates (4) and gate control instructions (5; Fig. 5). The gate control list comprises a set of individual gate control lists (7), each individual gate control list configured to control a respective gate and which comprises a sequence of entries (10), each entry comprising a duration of time (11; Fig. 11).