TSPC D Flip-Flop with Resistive Nodes for Leakage Control
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Solution Overview
Problem
Master-slave D-type flip-flops have larger size, slower operation speed, and higher power consumption, which limits their performance in integrated circuits, while true single-phase clock D flip-flops aim to address these issues with higher speed, low layout area, and low power consumption but are affected by leakage currents.
Innovation Solution
The design incorporates specific configurations of transistors and connecting devices, including resistive and short circuit elements, to manage the driving strengths of p-type and n-type transistors, reducing leakage currents and maintaining node voltages within acceptable levels, thereby ensuring correct operation of the D flip-flop.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If master-slave D-type flip-flop is used, then anti-noise capability is improved, but device size increases, operation speed decreases, and power consumption increases
Solution Approach 1:
The flip-flop is divided into distinct functional blocks: a first dynamic logic block for data latching, a second dynamic logic block for output generation, and complementary logic circuits. This segmentation allows each block to be optimized independently, achieving high speed while maintaining anti-noise capability through the master-slave architecture.
Solution Approach 2:
The patent employs dynamic logic circuits with clocked signal transmission and precharge/evaluate phases. The dynamic nature allows faster operation compared to static master-slave designs, while the clocked synchronization maintains the anti-noise properties of master-slave architecture.
2Productivity
If true single-phase clock D flip-flop is used, then operation speed and power consumption are improved, but leakage current increases
Solution Approach 1:
Weakly driven nodes are introduced as intermediary elements between the dynamic logic blocks. These nodes act as buffers that maintain voltage levels during floating states, preventing excessive leakage current while enabling the fast switching characteristics of dynamic logic.
Solution Approach 2:
The patent carefully controls transistor sizing and driving strengths to optimize the balance between speed and leakage. By adjusting the parameters of transistors in the dynamic logic blocks and signal transmission paths, the circuit achieves high-speed operation while keeping leakage currents at acceptable levels.
3Productivity
If transistor driving strengths are increased to improve speed, then operation speed is improved, but leakage current increases and node voltages become unstable
Solution Approach 1:
Different regions of the circuit have different transistor driving strengths optimized for their specific functions. The first and second dynamic logic blocks have appropriately sized transistors for their respective roles, with weakly driven nodes positioned at critical points to maintain voltage stability without requiring high driving strength throughout the entire circuit.
Data Source
AI summary
A true single-phase clock (TSPC) D flip-flop includes four stages. The four stages are serially connected between the input terminal and the output terminal of the TSPC D-type flip-flop. Each stage is selectively equipped with two connecting devices. One of the two connecting devices is a resistive element. The other of the two connecting devices is a short circuit element. When the node between two stages is in the floating state, the voltage change is slowed down by the resistive element. Consequently, the possibility of causing the function failure of the D-type flip-flop is minimized.