TSPC D Flip-Flop Topology for Floating-Node Voltage Stability
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Solution Overview
Problem
Master-slave D-type flip-flops have larger size, slower operation speed, and higher power consumption, which are limitations in integrated circuits, while dynamic circuits like true single-phase clock D flip-flops offer higher speed, low layout area, and low power consumption but are affected by leakage currents.
Innovation Solution
The design incorporates specific transistor configurations and connecting devices, including resistive and short circuit elements, to manage the driving strengths of transistors and reduce leakage currents, and optionally uses capacitors to mitigate the Miller effect, thereby maintaining node states effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If master-slave D-type flip-flop is used, then anti-noise capability is improved, but size increases, operation speed decreases and power consumption increases
Solution Approach 1:
The flip-flop is divided into two independent stages: a first stage for sampling the input signal during the high level of the clock signal, and a second stage for outputting the sampled signal during the low level of the clock signal. This segmentation allows each stage to be optimized independently, reducing overall complexity while maintaining reliability.
Solution Approach 2:
The patent employs dynamic logic circuits with clocked control signals that switch the circuit between different operational states. The clock signal dynamically controls the transmission gates and buffers to alternate between sampling and output modes, enabling high-speed operation with reduced power consumption compared to static master-slave designs.
2Productivity
If dynamic circuit is used, then operation speed is improved and power consumption is reduced, but leakage current increases
Solution Approach 1:
Transmission gates are introduced as intermediary elements between the input signal and the first buffer, and between the second buffer and the output. These transmission gates act as controlled switches that isolate floating nodes from direct leakage paths while maintaining signal integrity, thereby reducing leakage current without compromising operation speed.
Solution Approach 2:
The patent changes the operational parameters of the circuit by using complementary clock signals (CLK and CLK_bar) to control the switching behavior of transmission gates and buffers. By dynamically adjusting the conduction states of these elements based on clock phases, the circuit minimizes leakage current during idle periods while maintaining high-speed operation during active periods.
3Device complexity
If nodes are in floating state, then circuit operation is simplified, but voltage rise occurs and reliability decreases
Solution Approach 1:
The circuit is designed to pre-charge or pre-discharge nodes to predetermined voltage levels before they enter floating states. This preliminary action ensures that when nodes become floating, they start from a known stable voltage level, preventing unpredictable voltage rises and maintaining reliability without complicating the overall circuit operation.
Data Source
AI summary
A true single-phase clock (TSPC) D flip-flop includes four stages. The four stages are serially connected between the input terminal and the output terminal of the TSPC D-type flip-flop. Each stage is selectively equipped with two connecting devices. One of the two connecting devices is a resistive element. The other of the two connecting devices is a short circuit element. When the node between two stages is in the floating state, the voltage change is slowed down by the resistive element. Consequently, the possibility of causing the function failure of the D-type flip-flop is minimized.