TSPC D Flip-Flop Resistive Links for Floating-Node Stability
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Solution Overview
Problem
Master-slave D-type flip-flops have larger size, slower operation speed, and higher power consumption, which limits their performance in integrated circuits, while dynamic circuits like true single-phase clock D flip-flops offer higher speed, lower power consumption, and smaller layout area but are affected by leakage currents.
Innovation Solution
The design incorporates specific transistor configurations and connecting devices, including resistive and short circuit elements, to manage leakage currents by adjusting the driving strengths of transistors and using capacitors to mitigate the Miller effect, thereby reducing voltage rise and maintaining node states effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If master-slave D-type flip-flop is used, then anti-noise capability is improved, but size increases, operation speed decreases, and power consumption increases
Solution Approach 1:
The flip-flop is divided into two independent latches (first latch and second latch) that operate in different phases. The first latch samples data during one clock phase while the second latch holds the previous state, enabling seamless state transition without requiring the entire circuit to operate at the master-slave speed limit.
Solution Approach 2:
The patent employs dynamic logic gates (dynamic NAND gates and dynamic inverters) that utilize precharge and evaluate phases. During the precharge phase, nodes are prepared; during the evaluate phase, actual logic operations occur. This dynamic operation allows faster switching compared to static master-slave configurations.
2Reliability
If master-slave D-type flip-flop is used, then anti-noise capability is improved, but power consumption increases
Solution Approach 1:
The circuit uses periodic clock phases (first clock phase and second clock phase) to alternately activate different latches. During each phase, only the active latch consumes significant power while the other latch remains in a low-power hold state, reducing overall power consumption compared to master-slave where both stages are continuously active.
Solution Approach 2:
The patent converts the potentially harmful leakage current into a beneficial effect by using it to maintain the hold state in the inactive latch. The leakage current naturally preserves the stored state without requiring additional power, turning a disadvantage of dynamic logic into an advantage for power efficiency.
3Productivity
If dynamic circuit is used, then operation speed and power efficiency are improved, but leakage current affects operation
Solution Approach 1:
The patent introduces connecting devices (first connecting device and second connecting device) with controlled resistance values that act as intermediaries between the latches. These devices control the flow of leakage current, allowing it to maintain the hold state in the inactive latch while preventing it from causing erroneous state changes or function failure.
Solution Approach 2:
The patent optimizes the resistance values of the connecting devices to specific ranges that balance two opposing requirements: low enough to allow leakage current to maintain the hold state, but high enough to prevent leakage from causing function failure. This parameter optimization converts leakage from a harmful factor into a useful mechanism for state maintenance.
4Area of stationary object
If dynamic circuit is used, then layout area is reduced, but leakage current causes function failure
Solution Approach 1:
The patent applies different quality characteristics to different parts of the circuit. The connecting devices have specifically optimized resistance values that differ from typical logic gate characteristics. This local quality optimization ensures that leakage current is controlled appropriately in critical paths while maintaining the compact dynamic logic structure elsewhere, preventing function failure without sacrificing area efficiency.
Data Source
AI summary
A true single-phase clock (TSPC) D flip-flop includes four stages. The four stages are serially connected between the input terminal and the output terminal of the TSPC D-type flip-flop. Each stage is selectively equipped with two connecting devices. One of the two connecting devices is a resistive element. The other of the two connecting devices is a short circuit element. When the node between two stages is in the floating state, the voltage change is slowed down by the resistive element. Consequently, the possibility of causing the function failure of the D-type flip-flop is minimized.