TSPC Latch Topology With Symmetric Data Paths and Low Clock Power
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Solution Overview
Problem
Conventional latch circuits suffer from clock skew, asymmetrical setup/hold rise and fall times, and high clock power consumption due to asymmetrical input data paths and the use of multiple clock phases, which worsen metastability and increase layout area.
Innovation Solution
A True Single-Phase Clock (TSPC) latch design with symmetrical input data paths, utilizing a single clock signal to sense and latch data, featuring a balanced construction with feedback and feed-forward inverters to prevent undefined states and reduce metastability, while maintaining low clock power consumption and layout area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional latch circuits use asymmetrical input data paths with different transistor types (PMOS and NMOS), then the circuit can be implemented with standard transistor configurations, but the setup/hold rise and fall times become asymmetrical and metastability worsens
Solution Approach 1:
The patent applies asymmetry in reverse - it deliberately creates symmetrical input data paths where both rising and falling data signals traverse paths with identical transistor types and configurations. This symmetry ensures that setup and hold times are equal for both logic transitions, eliminating the metastability issues caused by asymmetrical rise and fall times in conventional designs.
2Adaptability or versatility
If conventional latch circuits generate complementary clock signals using an inverter, then clock signal availability is improved, but clock skew between rising and falling edges increases
Solution Approach 1:
The patent extracts and eliminates the clock inverter from the conventional latch circuit. By using a True Single-Phase Clock (TSPC) approach, the circuit operates with only the primary clock signal CK, removing the source of clock skew entirely while maintaining proper latch operation through single-phase clocked transistors.
3Ease of operation
If conventional latch circuits use multiple transistors coupled to clock signals (six transistors), then clock control functionality is achieved, but clock power consumption increases
Solution Approach 1:
The patent removes redundant clock-coupled transistors from the conventional six-transistor configuration. The TSPC latch uses only four transistors (two PMOS and two NMOS) that are coupled to the clock signal, eliminating two transistors and their associated clock switching activity, thereby reducing dynamic power consumption while maintaining essential clock control functionality.
4Device complexity
If conventional latch circuits use asymmetrical input data paths, then implementation simplicity is maintained, but layout area increases due to metastability mitigation requirements
Solution Approach 1:
The patent creates symmetrical input data paths where both rising and falling data signals travel through paths with identical transistor types, sizes, and configurations. This symmetry naturally balances the timing characteristics, eliminating the need for additional layout area dedicated to metastability mitigation techniques that would be required with asymmetrical paths.
Data Source
AI summary
A True Single Phase Clock (TSPC) latch design with symmetrical input data paths. A first input data path includes: a first NMOS transistor coupling a gate of a first PMOS transistor to VSS in response to a rising input data signal, and a second PMOS transistor having a gate coupled to a logic low (VSS) input clock signal, whereby the first and second PMOS transistors turn on to couple a data input node to VDD. A second input data path includes: a third PMOS transistor having a gate coupled to a falling input data signal (VSS), a fourth PMOS transistor having a gate coupled to a logic low (VSS) input clock signal, whereby the third and fourth PMOS transistors turn on to couple a gate of a second NMOS transistor to VDD, whereby the second NMOS transistor turns on to couple the data input node to VSS.