TSPL Clock Divider for Accurate GHz Signal Division
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Solution Overview
Problem
Conventional clock dividers based on static logic gates are inadequate for dividing clock signals above two gigahertz due to internal logic gate delays and set-up times that are slower than the clock signal period, making them unsuitable for modern high-frequency central processing units.
Innovation Solution
A true single phase logic clock divider employing dynamic logic, specifically True Single Phase Logic (TSPL), which uses NMOS MOSFETs and a single phase clock, allowing for reliable division of clock signals by increments of two, three, four, or six, and capable of operating at frequencies up to four gigahertz.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional static logic gates and flip-flops are used in clock dividers, then the circuit structure is simple and easy to manufacture, but the internal logic gate delays and set-up times are slower than the period of clock signals above two gigahertz, making them unsuitable for high-frequency operation
Solution Approach 1:
The patent employs dynamic logic gates (specifically true single phase logic - TSPL) instead of static logic gates. Dynamic logic uses transient signals and capacitive storage to achieve faster switching speeds, allowing the clock divider to operate reliably at frequencies above two gigahertz where static logic would fail due to excessive propagation delays
Solution Approach 2:
The invention changes the operational parameters of the logic gates by using dynamic switching mechanisms with reduced propagation delays. The TSPL gates utilize controlled charging and discharging of capacitive nodes to achieve sub-nanosecond switching times, enabling accurate division of high-frequency clock signals
2Productivity
If the clock frequency is increased to increase computing power, then the processing speed improves, but conventional clock dividers become too slow to accurately divide the clock signals
Solution Approach 1:
By implementing dynamic logic gates with transient operation modes, the clock divider achieves response times fast enough to keep pace with gigahertz-range clock signals, enabling the system to utilize higher clock frequencies for increased computing power without sacrificing division accuracy
3Speed
If static logic-based clock dividers are used, then the device complexity is low, but they cannot accurately divide clock signals with frequencies above two gigahertz
Solution Approach 1:
The patent accepts increased device complexity in the form of dynamic logic gate structures (TSPL) as a necessary trade-off to achieve the required operating speed. The dynamic gates incorporate capacitive storage elements and controlled switching networks that, while more complex than static gates, enable reliable operation at frequencies above two gigahertz
Data Source
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AI summary
There is provided a true single phase logic clock divider (20) that is configured to divide a clock signal (46) by increments of two, three, four, or six. Because the true single phase logic clock divider (20) is based on true single phase logic instead of static logic, the true single phase logic clock divider (20) is able to reliably divide clock signals (46) that could not reliably be divided by clock dividers based on static logic gates. There is also provided a method comprising receiving an input signal (46) with a frequency between 2.5 gigahertz and 4 gigahertz and producing an output signal (54) with a frequency approximately one-third of the frequency of the input signal.