3D IC Structure Using Through-Substrate Vias for High Density
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Solution Overview
Problem
Integrated circuits (ICs) face limitations in increasing functional density due to the inability to further reduce minimum feature size, necessitating alternative approaches such as vertical integration into three-dimensional ICs, where electronic devices are restricted to the front side of the semiconductor substrate, limiting density and performance.
Innovation Solution
Electronic devices are arranged on both the front and back sides of a semiconductor substrate with through-substrate vias (TSVs) to electrically couple them, allowing for a 3D IC configuration that enhances functional density, reduces size, and improves performance by shortening metal interconnect distances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If electronic devices are arranged only on the front side of the semiconductor substrate, then the manufacturing process is simpler, but the functional density is limited
Solution Approach 1:
The patent transitions from a two-dimensional arrangement (front side only) to a three-dimensional arrangement by utilizing both front and back sides of the semiconductor substrate. This dimensional expansion allows electronic devices to be distributed across multiple surfaces, effectively doubling the available area for device placement and significantly increasing functional density without requiring further reduction in feature size.
Solution Approach 2:
The patent implements a nested structure where through-substrate vias penetrate the semiconductor substrate to electrically connect electronic devices on the front side with those on the back side. This nesting approach allows the back-side devices to be integrated into the overall circuit architecture, creating a compact three-dimensional configuration that maximizes functional density within the substrate volume.
2Speed
If through-substrate vias are used to connect front and back sides, then metal interconnect distance is shortened and performance is improved, but manufacturing complexity increases
Solution Approach 1:
The patent forms through-substrate vias during the semiconductor manufacturing process before final device assembly. By preparing these conductive pathways in advance, the patent enables direct electrical connection between front and back side devices, significantly reducing metal interconnect distance and improving signal transmission speed. The preliminary formation of vias integrates seamlessly into the fabrication flow, making the additional complexity manageable.
3Quantity of substance
If minimum feature size is reduced to increase functional density, then more devices can be integrated, but process limitations prevent further reduction
Solution Approach 1:
Instead of continuing to reduce minimum feature size in the lateral direction, the patent exploits the vertical dimension by utilizing both front and back surfaces of the substrate. This approach bypasses the lithography process limitations that prevent further feature size reduction, achieving increased functional density through three-dimensional device distribution rather than two-dimensional scaling.
Data Source
AI summary
An integrated circuit (IC) provides high performance and high functional density. A first back-end-of-line (BEOL) interconnect structure and a second BEOL interconnect structure are respectively under and over a semiconductor substrate. A first electronic device and a second electronic device are between the semiconductor substrate and respectively a bottom of the first BEOL interconnect structure and a top of the second BEOL interconnect structure. A through substrate via (TSV) extends through the semiconductor substrate, from the first BEOL interconnect structure to the second BEOL interconnect structure. A method for manufacturing the IC is also provided.