TSV Abnormality Detection via AC Signal Delay Comparison

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Solution Overview

Problem

The challenge in semiconductor devices is determining abnormal AC signal transfer characteristics of through silicon vias (TSVs) after packaging stacked chips, as abnormal TSVs can lead to deteriorated signal transfer, affecting chip operation despite normal DC signal transfer characteristics.

Innovation Solution

A semiconductor device with a reference TSV set and a determination unit that generates reference delay information and compares initial test signals with signals delayed by individual TSVs to identify abnormality, ensuring reliable AC signal transfer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If TSV abnormality determination is performed before packaging, then manufacturing precision can be improved, but device complexity increases due to additional testing equipment and processes

Engineering Contradiction:
ImproveTSV abnormality determination accuracyVSAvoidtesting equipment and process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent performs TSV abnormality determination during the packaging process itself rather than before or after. The determination unit is integrated into the packaging device, allowing abnormality detection to occur as a preliminary action within the existing packaging workflow, avoiding the need for separate pre-packaging or post-packaging testing equipment

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces a determination unit as an intermediary component within the packaging device that automatically detects TSV abnormalities by analyzing signal transfer characteristics. This intermediary unit bridges the gap between packaging operations and quality assessment, eliminating the need for complex external testing equipment

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If TSV abnormality is detected after packaging, then productivity is improved by avoiding rework, but reliability deteriorates because abnormal TSVs cannot be identified before chip operation

Engineering Contradiction:
Improvepackaging throughputVSAvoidAC signal transfer reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The determination unit provides real-time feedback on TSV abnormality during the packaging process. By analyzing the AC signal transfer characteristics of each TSV as chips are being packaged, the system immediately identifies abnormal TSVs and can flag affected products for rework or rejection, maintaining both high productivity and reliability

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The packaging device performs self-inspection by integrating the determination unit that automatically tests TSV functionality during packaging. The system uses its own packaging infrastructure to conduct quality assessment, eliminating the need for separate reliability testing stages while maintaining product quality

Inventive Principle:
Principle #25Self-service

3Ease of operation

If DC signal transfer characteristic testing is performed, then ease of operation is improved, but measurement precision deteriorates because DC testing cannot detect AC signal transfer abnormalities

Engineering Contradiction:
Improvetesting simplicityVSAvoidAC signal transfer characteristic accuracy
Core Design Contradiction:
Ease of operationVSMeasurement precision

Solution Approach 1:

The determination unit changes the testing parameter from DC signal characteristics to AC signal transfer characteristics. By applying AC test signals and measuring their transfer through the TSVs, the system can detect abnormalities such as open gaps and voids that are invisible to DC testing, thereby improving measurement precision without significantly complicating the testing operation

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS9208898B2Semiconductor device and operating method of semiconductor device
Publication Date: 2015.12.08 SK HYNIX INC
  • US9208898B2 patent drawing
  • US9208898B2 patent drawing
  • US9208898B2 patent drawing

AI summary

A semiconductor device includes a plurality of stacked chips, a reference through silicon via (TSV) set passing through the plurality of stacked chips, a plurality of TSVs passing through the plurality of stacked chips, a reference delay information generation unit suitable for generating a reference delay information indicating an amount of delay of the reference TSV set and a determination unit suitable for determining abnormality of the plurality of TSVs by comparing a first test signal with each of a plurality of second test signals, wherein the first test signal is an initial test signal delayed by an amount of delay corresponding to the reference delay information, and wherein each of the plurality of second test signals is the initial test signal delayed by corresponding one of the plurality of TSVs.