TSV Semiconductor Package With Aligned Adhesive Layer
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Solution Overview
Problem
Current semiconductor packaging techniques face challenges in simplifying the forming process and achieving precise adhesion between semiconductor chips, particularly in mounting multiple chips in a single package while maintaining efficient electrical connections and thermal management.
Innovation Solution
A semiconductor package design featuring through-silicon vias (TSVs) with adhesive layers that align with the side surfaces of upper semiconductor chips, connecting them to the substrate and enabling efficient electrical and thermal interfaces, along with the use of thermal interface materials and under-fill materials for enhanced thermal management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional semiconductor packaging techniques are used to mount multiple chips, then electrical connections and thermal management can be achieved, but the forming process becomes complex and adhesion between chips is imprecise
Solution Approach 1:
The adhesive layer is pre-formed on the lower semiconductor chip before mounting the upper chip. This preliminary preparation ensures precise adhesion positioning and simplifies the overall mounting process, as the adhesive is already in place to receive the upper chip without requiring complex real-time alignment procedures
Solution Approach 2:
The adhesive layer acts as an intermediary element between the lower semiconductor chip and the upper semiconductor chip. It facilitates precise adhesion and electrical connection while accommodating slight misalignments, thereby simplifying the forming process and improving manufacturing precision simultaneously
2Manufacturing precision
If adhesive layer side surfaces are aligned with upper chip side surfaces, then precise adhesion is achieved, but the structure becomes more complex
Solution Approach 1:
The adhesive layer is applied with specific local characteristics - its side surfaces are aligned with the side surfaces of the upper semiconductor chip only in the regions where precise adhesion is required. This localized alignment approach achieves manufacturing precision without requiring the entire package structure to be complex
3Reliability
If multiple connection terminals are used to connect TSVs and active layer, then electrical connectivity is improved, but the forming process becomes more complex
Solution Approach 1:
The adhesive layer serves dual functions: it provides mechanical adhesion between chips and simultaneously facilitates electrical connection through embedded connection terminals. This merging of mechanical and electrical functions improves reliability while simplifying the forming process, as a single layer accomplishes both tasks
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design simplifies the forming process, ensures precise adhesion and electrical connectivity between semiconductor chips, and improves thermal management, making it suitable for lightweight, thin, and small-sized electronic systems.
Implementation Method 1
An adhesive layer is between the first semiconductor chip and the active layer
Implementation Method 2
A thermal interface material (TIM) layer may be on the second semiconductor chip. A heat slug may be on the TIM layer
Implementation Method 3
An under-fill material may be provided between the substrate and the first semiconductor chip
Data Source
AI summary
A semiconductor package includes a first semiconductor chip on a substrate and having a plurality of through-silicon vias (TSVs). A second semiconductor chip having an active layer is on the first semiconductor chip. An adhesive layer is between the first semiconductor chip and the active layer. Connection terminals extend through the adhesive layer and are connected to the TSVs and the active layer. Side surfaces of the adhesive layer are aligned with side surfaces of the second semiconductor chip.