Through-Substrate Via Adhesive Bonding for 3D IC Yield
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Solution Overview
Problem
The fabrication of three-dimensional integrated circuit devices requires additional manufacturing steps to join die and wafers together, increasing costs and the risk of defects, which reduces device yield.
Innovation Solution
The method involves bonding a semiconductor wafer and an integrated circuit die using an adhesive material, forming through-substrate vias with conductive material for electrical interconnection, and segmenting the wafer into individual devices, which reduces manufacturing steps and enhances reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional manufacturing steps are used to join die and wafers together, then electrical interconnectivity between stacked die and wafers is achieved, but device yield decreases due to increased risk of defects
Solution Approach 1:
The patent combines the die attachment and electrical interconnection functions into a single integrated structure. The adhesive material serves dual purposes: mechanically bonding the die to the wafer and providing the conductive path for electrical signals through the substrate, thereby reducing the number of separate manufacturing steps and minimizing defect risks
Solution Approach 2:
The adhesive material is designed to perform multiple functions simultaneously: it acts as a bonding agent for mechanical attachment, provides electrical conductivity for signal transmission, and serves as an insulating layer in certain configurations. This multi-functionality eliminates the need for separate conductive via structures and reduces process complexity
2Reliability
If additional manufacturing steps are used to join die and wafers together, then electrical interconnectivity is achieved, but manufacturing costs increase
Solution Approach 1:
By merging die attachment and electrical interconnection into a single step using the adhesive material, the patent eliminates multiple costly processing steps including separate via formation, conductive material deposition, and alignment procedures, thereby reducing overall manufacturing costs while maintaining reliable electrical connectivity
Solution Approach 2:
The adhesive material is formulated to self-align and self-position the die relative to the wafer during attachment, eliminating the need for complex external alignment systems and reducing manufacturing costs. The material's inherent properties enable automatic positioning and bonding in a single operation
3Reliability
If adhesive material allows lateral expansion during bonding, then bonding reliability is improved, but via formation precision may be affected
Solution Approach 1:
The adhesive material is applied in a controlled manner before die attachment, with pre-defined patterns and dimensions that account for expected lateral expansion. This preliminary configuration ensures that even as the material expands during bonding, the final via positions remain precisely aligned with the intended electrical connection points
Solution Approach 2:
The adhesive material's physical parameters are carefully controlled during processing, including its expansion characteristics, viscosity, and curing properties. By adjusting these parameters, the material achieves optimal lateral expansion for reliable bonding while maintaining sufficient dimensional stability to preserve via formation precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the fabrication process, reduces costs, and enhances the reliability and yield of three-dimensional integrated circuit devices by providing efficient electrical interconnectivity between stacked die and wafers.
Implementation Method 1
bonding a semiconductor wafer and an integrated circuit die using an adhesive material
Implementation Method 2
Through-substrate vias (TSV) furnish electrical interconnectivity to electronic components formed in the semiconductor wafer and the integrated circuit die
Data Source
AI summary
Semiconductor devices are described that have a through-substrate via formed therein. In one or more implementations, the semiconductor devices include a semiconductor wafer and an integrated circuit die bonded together with an adhesive material. The semiconductor wafer and the integrated circuit die include one or more integrated circuits formed therein. The integrated circuits are connected to one or more conductive layers deployed over the surfaces of the semiconductor wafer and an integrated circuit die. A via is formed through the semiconductor wafer and the patterned adhesive material so that an electrical interconnection can be formed between the integrated circuits formed in the semiconductor wafer and the integrated circuits formed in the integrated circuit die. The via includes a conductive material that furnishes the electrical interconnection between the semiconductor wafer and the integrated circuit die.