TSV Dielectric Liner Air-Gap Structure for Lower Parasitic Capacitance

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Solution Overview

Problem

The challenge in semiconductor structures is the increase in parasitic coupling capacitance and power consumption due to the parasitic coupling capacitance formed by through semiconductor vias (TSVs) and the semiconductor substrate, which is exacerbated by the dielectric liner.

Innovation Solution

Incorporating a plurality of discontinuous air gaps in the semiconductor substrate extending away from the dielectric liner surrounding the TSVs, which reduces the area of the semiconductor substrate acting as a capacitor electrode and alleviates stress.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a dielectric liner surrounds the TSV between the TSV and semiconductor substrate, then electrical insulation is provided, but parasitic coupling capacitance increases

Engineering Contradiction:
Improveelectrical insulationVSAvoidparasitic coupling capacitance
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The continuous semiconductor substrate surrounding the TSV is segmented by introducing discontinuous air gaps that divide the substrate into separate regions. This segmentation reduces the effective area of the substrate acting as a capacitor electrode, thereby reducing parasitic coupling capacitance while maintaining electrical insulation through the dielectric liner.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Air gaps are introduced into the semiconductor substrate, creating a porous structure around the TSV. These air gaps have lower dielectric constant compared to the semiconductor substrate material, which reduces the parasitic coupling capacitance formed between the TSV and substrate while the dielectric liner maintains electrical insulation.

Inventive Principle:
Principle #31Porous materials

2Object-generated harmful factors

If discontinuous air gaps are introduced in the semiconductor substrate adjacent to the dielectric liner, then parasitic capacitance is reduced, but manufacturing complexity increases

Engineering Contradiction:
Improveparasitic capacitanceVSAvoidmanufacturing complexity
Core Design Contradiction:
Object-generated harmful factorsVSDevice complexity

Solution Approach 1:

The air gaps are formed preliminary to final TSV completion, during the via formation process itself. By etching air gap regions into the substrate before or during TSV formation, and then sealing them with dielectric material, the structure is prepared in advance, reducing the need for complex post-processing steps.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The dielectric liner serves multiple functions: it provides electrical insulation between the TSV and substrate, and it also seals the air gaps formed in the substrate. This multi-functionality reduces manufacturing complexity by eliminating the need for separate sealing structures.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Stress or pressure

If air gaps extend away from the dielectric liner, then stress relief is achieved, but structural complexity increases

Engineering Contradiction:
Improvestress reliefVSAvoidstructural complexity
Core Design Contradiction:
Stress or pressureVSDevice complexity

Solution Approach 1:

Air gaps are extended in the vertical dimension away from the dielectric liner into the substrate, creating a three-dimensional stress relief structure. This vertical extension allows stress to be relieved through the depth of the substrate without requiring complex lateral structures, achieving stress relief while maintaining relatively simple planar geometry.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The implementation of air gaps effectively lowers parasitic capacitance by up to 40.8% and provides stress relief in the semiconductor substrate, thereby improving the performance of integrated circuit structures.

Implementation Method 1

A parasitic coupling capacitance is formed by the TSV conductors and the semiconductor substrate with the dielectric liner therebetween

Methodology Applied
Scientific EffectParasitic capacitance: Capacitance

Implementation Method 2

the air gaps extend away from the dielectric liner to reduce the area of the semiconductor substrate acting as a capacitor electrode and to provide stress relief

Methodology Applied
Scientific EffectStress relief: Stress Relaxation

Data Source

PatentUS12451411B2Structure with air gaps extending from dielectric liner around through semicondcutor via
Publication Date: 2025.10.21 GLOBALFOUNDRIES US INC
  • US12451411B2 patent drawing
  • US12451411B2 patent drawing
  • US12451411B2 patent drawing

AI summary

A structure includes a through semiconductor via (TSV) in a semiconductor substrate, and a dielectric liner surrounding the TSV and between the TSV and the semiconductor substrate. A plurality of discontinuous air gaps is in the semiconductor substrate extending away from the dielectric liner, e.g., radially. The discontinuous air gaps reduce the parasitic coupling capacitance and relieve stress in the semiconductor substrate.