TSV Air Liner Structure for Lower Parasitic Capacitance
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Solution Overview
Problem
Conventional semiconductor fabrication methods lead to excessive parasitic capacitance in 3-dimensional integrated circuits (3DICs), which affects thermal dissipation and performance.
Innovation Solution
Incorporation of air liners as a novel TSV liner to reduce parasitic capacitance by utilizing air's low dielectric constant, which is achieved through selective etching processes to create air gaps between the substrate and TSV structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional fabrication methods are used to create through-substrate vias, then the manufacturing process is simple and straightforward, but excessive parasitic capacitance is generated which degrades device performance
Solution Approach 1:
The patent extracts the dielectric material from the via region to create an air liner (air gap) between the substrate and the via structure. This removal of dielectric material eliminates the source of parasitic capacitance while maintaining the structural integrity and electrical functionality of the through-substrate via connection.
Solution Approach 2:
The patent changes the dielectric parameter of the via region from a solid dielectric material to air (which has a dielectric constant of approximately 1.0). This parameter change dramatically reduces the parasitic capacitance formed between conductive elements, thereby improving device performance without complicating the fabrication process.
2Speed
If air liners are incorporated to reduce parasitic capacitance, then device speed and performance increase, but the fabrication process becomes more complex requiring selective etching
Solution Approach 1:
The patent performs preliminary action by depositing a sacrificial liner structure before forming the through-substrate via. This pre-deposited liner is then selectively removed to create the air gap, allowing the air liner formation to be integrated into the existing fabrication sequence without requiring major process reorganization or additional complex steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Reduces parasitic capacitance, thereby increasing the speed and performance of 3DICs by lowering the dielectric constant and time constant.
Implementation Method 1
reduces parasitic capacitance, thereby increasing the speed and performance of 3DICs by lowering the dielectric constant and time constant
Data Source
AI summary
A first conductive pad disposed over a first side of a substrate in a first direction. A second conductive pad is disposed over a second side of the substrate in the first direction. A through-substrate via (TSV) extends into the substrate in the first direction. The TSV is disposed between the first conductive pad and the second conductive pad in the first direction. An air liner disposed between the TSV and the substrate in a second direction different from the first direction.