TSV Alignment in Semiconductor Substrate Stacks
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Solution Overview
Problem
Existing methods for producing front-to-front stacked semiconductor substrates face challenges in aligning connecting vias with TSV structures, leading to misalignment and limited connection, and the cost of photo procedures for patterning the backside of wafers, which affects the resistivity and efficiency of TSV/backside via structures.
Innovation Solution
The process involves etching TSV structures before the contact layer, coating with a dielectric liner, filling with sacrificial material, and using a dielectric etch stop layer, followed by planarization and removal of sacrificial material to improve alignment and connection efficiency, and reducing the cost by optimizing the use of high-quality dielectrics and conductive materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If connecting vias are etched into the backside of a thinned wafer after thinning, then TSV structures can be formed, but misalignment with prior formed TSV structures occurs and connection is limited
Solution Approach 1:
The patent applies preliminary action by forming the backside via openings and applying the dielectric liner to the TSV structures before wafer bonding. This sequence ensures that the TSV structures are pre-prepared with proper alignment features and protective layers, allowing for precise alignment during subsequent bonding without requiring post-bonding via formation that would compromise alignment precision.
Solution Approach 2:
The patent segments the TSV structure formation into distinct phases: forming openings in the first substrate, coating dielectric liner, filling with sacrificial material, and then bonding. This segmentation allows each step to be optimized independently, particularly enabling precise alignment of the backside via openings with the TSV structures before the irreversible bonding step.
2Manufacturing precision
If the diameter of backside via structure is smaller than TSV, then alignment is tighter, but sacrificial material removal becomes difficult and resistivity increases
Solution Approach 1:
The patent introduces a dielectric liner as an intermediary layer between the TSV structure and the sacrificial material. This liner provides a protective interface that facilitates complete sacrificial material removal while maintaining structural integrity. The liner acts as a mediator that allows the backside via to effectively clear the TSV structure without direct mechanical contact that would cause damage or incomplete removal.
Solution Approach 2:
The patent changes the physical and chemical parameters of the TSV structure by coating it with a dielectric liner and filling it with sacrificial material that has different etch characteristics. This parameter change enables selective removal of the sacrificial material through the liner, achieving complete clearance while maintaining the electrical connection pathway with reduced resistivity.
3Manufacturing precision
If photo procedures are used to pattern the backside of the wafer, then via structures can be formed, but manufacturing cost increases
Solution Approach 1:
The patent applies universality by using a dielectric liner that serves multiple functions: it protects the TSV structure during processing, enables precise patterning of the backside via openings, and facilitates complete sacrificial material removal. This multi-functional approach eliminates the need for separate photo procedure steps, reducing manufacturing cost while maintaining patterning precision through the liner's inherent structural guidance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the alignment and connectivity of TSV structures with the backside via, improving the electrical interconnection and reducing the resistivity and cost associated with the photo procedures, thereby increasing the efficiency and reliability of the semiconductor substrate stacking process.
Implementation Method 1
coating with a dielectric liner
Implementation Method 2
filling with sacrificial material
Implementation Method 3
using a dielectric etch stop layer
Data Source
AI summary
A method of manufacturing a semiconductor substrate structure for use in a semiconductor substrate stack system is presented. The method includes a semiconductor substrate which includes a front-face, a backside, a bulk layer, an interconnect layer that includes a plurality of inter-metal dielectric layers sandwiched between conductive layers, a contact layer that is between the bulk layer and the interconnect layer, and a TSV structure commencing between the bulk layer and the contact layer and terminating at the backside of the substrate. The TSV structure is electrically coupled to the interconnect layer and the TSV structure is electrically coupled to a bonding pad on the backside.