TSV Alignment Trench Eliminates Zero-Mark Layer
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Solution Overview
Problem
Conventional manufacturing processes for aligning redistribution layers (RDL) with through-silicon via (TSV) contacts in semiconductor devices face reliability issues and increased costs due to the use of extra zero-mark layers, which can lead to wafer dicing cracks and higher production expenses.
Innovation Solution
The proposed solution involves forming a substrate with TSV openings and alignment trenches, lined with a dielectric liner, where the RDL is patterned using a reticle aligned with an alignment mark, eliminating the need for a zero-mark layer and integrating alignment mark formation with TSV contact and liner formation, thereby simplifying the process and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If an extra zero-mark layer is used to assist alignment of conductive lines with TSV contacts, then alignment precision is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent combines the alignment mark formation with the TSV contact and liner formation processes. The alignment mark is created within the same trench structure as the TSV contact, eliminating the need for a separate zero-mark layer. This merging of functions reduces process complexity while maintaining alignment precision through the integrated alignment mark that is formed simultaneously with the TSV structure.
2Manufacturing precision
If an extra zero-mark layer is used to assist alignment, then alignment precision is improved, but manufacturing cost increases
Solution Approach 1:
The alignment mark is formed as part of the TSV contact structure using the same trench formation, liner deposition, and conductive filling processes. This consolidation eliminates the need for additional materials and process steps associated with a separate zero-mark layer, thereby reducing manufacturing cost while maintaining alignment precision through the integrated alignment feature.
3Manufacturing precision
If conventional processes with zero-mark layer are used, then alignment is assisted, but reliability deteriorates due to wafer dicing cracks
Solution Approach 1:
The alignment mark is integrated within the TSV contact trench structure, sharing the same dielectric liner and conductive fill. This integration ensures that the alignment mark and TSV contact are formed as a unified structure, eliminating the need for separate zero-mark layer processes that can introduce stress and cause dicing cracks, thereby improving wafer reliability while maintaining alignment capability.
Data Source
AI summary
Devices and methods for forming a device are disclosed. The method includes providing a substrate having first and second surfaces. At least one through silicon via (TSV) opening is formed in the substrate. The TSV opening extends through the first and second surfaces of the substrate. An alignment trench corresponding to an alignment mark is formed in the substrate. The alignment trench extends from the first surface of the substrate to a depth shallower than a depth of the TSV opening. A dielectric liner layer is provided over the substrate. The dielectric liner layer at least lines sidewalls of the TSV opening. A conductive layer is provided over the substrate. The conductive layer fills at least the TSV opening to form TSV contact. A redistribution layer (RDL) is formed over the substrate. The RDL layer is patterned using a reticle to form at least one opening which corresponds to a TSV contact pad. The reticle is aligned using the alignment mark in the substrate.