TSV Antenna Protection Circuit Using Complementary Diode-Connected Transistors
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Solution Overview
Problem
The manufacturing process of integrated circuits (ICs) faces challenges with plasma-induced gate oxide damage, known as the 'antenna effect,' which occurs due to electrical charges accumulating on conductive patterns or vias, leading to breakdown of the gate dielectric material and damage to transistors, particularly during the formation of Through Substrate Vias (TSVs) in 3D IC integration.
Innovation Solution
Incorporating an antenna effect protection circuit within the IC device that utilizes both P-type and N-type transistors, with their gates, sources, and drains electrically coupled together, forming diode structures to protect functional transistors from damage during manufacturing. This configuration improves chip area efficiency and reduces routing efforts by Automated Placement and Routing (APR) tools.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If antenna effect protection circuits are added to protect transistors from plasma-induced gate oxide damage, then transistor reliability is improved, but device complexity increases
Solution Approach 1:
The patent combines P-type and N-type transistors into a single integrated protection circuit unit. The P-type transistor protects against positive plasma charges while the N-type transistor protects against negative plasma charges, merging multiple protection functions into one compact structure that reduces overall device complexity while maintaining comprehensive protection.
Solution Approach 2:
The protection circuit is designed to handle both positive and negative plasma charges simultaneously through the complementary P-type and N-type transistors. This multi-functional design allows a single circuit structure to provide comprehensive protection against different types of plasma-induced damage, improving reliability without proportionally increasing complexity.
2Reliability
If both P-type and N-type transistors are used in the protection circuit, then protection effectiveness against plasma charges is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies different transistor types (P-type and N-type) in specific locations within the protection circuit, each optimized for handling specific plasma charge polarities. This local quality approach ensures that each transistor operates in its optimal performance range, improving overall protection effectiveness while using standard manufacturing processes for each transistor type.
3Object-affected harmful factors
If antenna protection circuits are implemented, then transistor damage from plasma charges is reduced, but chip area utilization decreases
Solution Approach 1:
The protection circuit merges P-type and N-type transistors into a compact integrated structure that occupies minimal chip area. By combining multiple protection functions into a single unit rather than using separate protection circuits for each transistor type, the design reduces the total area required while maintaining comprehensive protection against plasma-induced damage.
Data Source
AI summary
An integrated circuit (IC) device includes a first substrate, a through substrate via (TSV) in the first substrate, and a first antenna effect protection circuit over the first substrate and electrically coupled to the TSV. The first antenna effect protection circuit includes at least one first transistor of a first type, and at least one second transistor of a second type different from the first type. A gate terminal, a first terminal and a second terminal of each of the at least one first transistor and the at least one second transistor are electrically coupled together, and to the TSV.