TSV Antifuse Power Gating for 3D IC Area Reduction
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Solution Overview
Problem
Existing semiconductor chips face challenges with power and performance due to area consumption by switched transistors, which also experience IR-drop when active and leakage when inactive, limiting the density of active circuits in planar designs.
Innovation Solution
The implementation of programmable through-silicon vias (TSVs) acting as antifuses to selectively couple a functional ground layer to a grounded semiconductor substrate, replacing switched transistors and allowing power gating by blowing the antifuse material with a program voltage to connect the functional circuit to ground.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If switched transistors are used for power gating in planar IC designs, then power control functionality is achieved, but chip area consumption increases and power losses (IR-drop and leakage) occur
Solution Approach 1:
The patent transitions from planar (2D) power gating using switched transistors to three-dimensional power gating using through-silicon vias (TSVs) that extend vertically through the substrate. This dimensional change allows power gating functionality to be implemented in the vertical dimension, freeing up horizontal chip area while maintaining effective power control through the substrate thickness.
Solution Approach 2:
The invention extracts the power gating functionality from the planar transistor layer and relocates it to vertical TSV structures that pass through the substrate. By separating the power gating function into dedicated vertical conduits, the design eliminates the need for switched transistors in the active circuit plane, reducing area consumption and interference with functional circuits.
2Reliability
If switched transistors are used for power gating, then power control is achieved, but power losses occur due to IR-drop when active and leakage when inactive
Solution Approach 1:
The patent replaces the mechanical/electronic switching mechanism (transistors) with a structural/conductive mechanism (TSVs with antifuse materials). The TSVs provide direct conductive paths through the substrate, and the antifuse materials enable or disable conduction through structural changes rather than active switching, eliminating IR-drop and leakage associated with transistor operation.
Solution Approach 2:
The antifuse material acts as an intermediary between the TSV and the power control function. This material can be in a high-resistance state to block power (replacing the off-state transistor) or transformed into a low-resistance state to enable power flow (replacing the on-state transistor), providing power gating without the parasitic losses of transistor switching.
3Ease of manufacture
If planar IC design is used, then manufacturing simplicity is maintained, but the density of active circuits is limited
Solution Approach 1:
The patent extends the circuit architecture from two-dimensional planar layout to three-dimensional structures by incorporating TSVs that traverse the substrate thickness. This enables vertical interconnects and stacking of functional layers, dramatically increasing circuit density without complicating the fundamental manufacturing processes, as TSV formation uses standard semiconductor fabrication techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces chip area consumption, improves power gating efficiency, and enhances power delivery to functional circuits, addressing the limitations of planar designs by enabling dense three-dimensional IC structures with reduced power losses.
Implementation Method 1
an antifuse material is deposited between the back-end surface of the TSV and the semiconductor substrate. The antifuse material is configured to insulate the TSV from the semiconductor substrate. A functional ground layer is insulated from the semiconductor on insulator structure, and electrically coupled with the TSV and the functional circuit. The functional ground layer is configured to conduct a program voltage to the TSV to cause a portion the antifuse material to migrate away from the TSV, thereby electrically connecting the functional circuit to the ground.
Data Source
AI summary
A semiconductor chip includes a semiconductor on insulator structure having a frontside and a backside. The chip includes a circuit in the semiconductor layer at the frontside. The circuit is isolated from a substrate. The chip includes a through silicon via (TSV) having a front-end, a back-end, and a lateral surface. The TSV is in the semiconductor layer and buried oxide layer and the front-end surface of the TSV is substantially parallel to the frontside of the semiconductor layer. An antifuse is deposited between the back-end of the TSV and the substrate. The antifuse insulates the TSV from the substrate. A ground layer is insulated from the semiconductor on insulator structure, and is coupled with the TSV and the circuit. The ground layer conducts a program voltage to the TSV to cause a portion the antifuse to migrate away from the TSV, thereby connecting the circuit to the ground.