Backside Wafer Protection for TSV Copper Contamination

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Solution Overview

Problem

Copper contamination at the backside surface of silicon wafers during through silicon via (TSV) exposure and reactive ion etch (RIE) poses a significant challenge, especially after wafer thinning, leading to semiconductor device failure due to lack of gettering layer and poor step coverage of the barrier layer.

Innovation Solution

A method involving the formation of a backside wafer protection layer by exposing a passivation layer surrounding the TSV, followed by a silicon composite layer and a hardmask layer, which are then selectively removed to expose a contact for the TSV, while also forming an oxide layer and using chemical mechanical polishing to prevent copper contamination.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If wafer thinning is performed to enable TSV exposure, then manufacturing precision is improved, but copper contamination occurs at the backside surface

Engineering Contradiction:

ImproveTSV exposure precisionVSAvoidcopper contamination

Core Design Contradiction:

Manufacturing precisionVSObject-affected harmful factors

Solution Approach 1:

A protective layer is formed at the backside surface of the wafer before TSV exposure and RIE processes. This preliminary protective action prevents copper contamination during subsequent processing steps, particularly addressing the contamination issue that arises after wafer thinning when TSVs are exposed.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The protective layer acts as an intermediary barrier between the copper-containing TSV structures and the backside surface of the wafer. This intermediary layer prevents direct contact and ion migration, thereby blocking copper contamination while allowing the TSV exposure process to proceed with high precision.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Ease of manufacture

If barrier layer step coverage is reduced to simplify manufacturing, then ease of manufacture is improved, but copper contamination increases due to poor coverage

Engineering Contradiction:

Improvemanufacturing simplicityVSAvoidcopper contamination

Core Design Contradiction:

Ease of manufactureVSObject-affected harmful factors

Solution Approach 1:

The protective function is segmented into a separate, dedicated protective layer rather than relying solely on the barrier layer's step coverage. This segmentation allows the barrier layer to be simpler while the protective layer provides comprehensive coverage against copper contamination.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The solution changes the approach from optimizing barrier layer geometry (step coverage) to adding a separate protective layer with different material properties. This parameter change enables easier manufacturing of the barrier layer while the protective layer provides the necessary contamination prevention.

Inventive Principle:

Principle #35Parameter changes

3Reliability

If multiple protective layers are added to prevent copper contamination, then reliability is improved, but device complexity increases

Engineering Contradiction:

Improvecontamination preventionVSAvoidprocess complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The protective function is extracted as a separate, dedicated layer rather than being integrated into the barrier layer structure. This extraction allows for optimized contamination prevention while maintaining clear functional separation, reducing overall process complexity compared to attempting to achieve both barrier and protective functions in a single complex layer.

Inventive Principle:

Principle #2Taking out (Extraction)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method effectively prevents copper contamination at the wafer backside during TSV exposure, ensuring the integrity of semiconductor devices and enabling their use in highly integrated applications such as microprocessors and smartphones.

Implementation Method 1

forming a silicon composite layer over the exposed passivation layer and over a bottom surface of the silicon substrate

Methodology Applied

Scientific EffectDeposition: Deposition (physical)

Implementation Method 2

planarizing the hardmask layer by chemical mechanical polishing, wet etching, or a combination thereof

Methodology Applied

Scientific EffectChemical mechanical polishing:

Data Source

PatentUS9230886B2Method for forming through silicon via with wafer backside protection

Publication Date: 2016.01.05 GLOBALFOUNDRIES SINGAPORE PTE LTD

AI summary

Semiconductor devices with through silicon vias (TSVs) are formed without copper contamination. Embodiments include exposing a passivation layer surrounding a bottom portion of a TSV in a silicon substrate, forming a silicon composite layer over the exposed passivation layer and over a bottom surface of the silicon substrate, forming a hardmask layer over the silicon composite layer and over the bottom surface of the silicon substrate, removing a section of the silicon composite layer around the bottom portion of the TSV using the hardmask layer as a mask, re-exposing the passivation layer, and removing the hardmask layer and the re-exposed passivation layer to expose a contact for the bottom portion of the TSV.