Through Silicon Vias Backside Connection Electroplating

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Solution Overview

Problem

Existing integrated circuits with through-silicon vias for backside connection of flexible circuits face challenges in efficiently forming and connecting metal interconnects within the IC die, which affects the reliability and performance of proximity sensor devices and display devices.

Innovation Solution

The method involves forming laser-drilled vias through the IC substrate from the front side and using a single electroplating process to create metal interconnects between metal pads, which are then exposed on the back side for connection with a flexible circuit, improving electrical performance and reducing resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If laser drilling and electroplating are performed separately for through-silicon vias, then manufacturing precision can be maintained, but manufacturing complexity and process time increase

Engineering Contradiction:
Improvemanufacturing process simplicityVSAvoidvia formation precision
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent combines laser drilling and electroplating operations into an integrated through-silicon via formation process. The laser drilling creates the via hole while simultaneously preparing the surface for electroplating, and the electroplating process fills the via in a continuous operation. This merging of previously separate processes reduces manufacturing complexity and process time while maintaining via formation precision through coordinated process parameters.

Inventive Principle:
Principle #5Merging (Combining)

2Reliability

If multiple metal layers are connected through through-silicon vias, then electrical connectivity is improved, but device complexity increases

Engineering Contradiction:
Improveelectrical connection reliabilityVSAvoidinterconnect structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the interconnect structure into distinct functional components: through-silicon vias for vertical penetration, metal fills for electrical conduction, and pads for external connection. Each segment performs a specific function, allowing complex multi-layer connectivity to be achieved through standardized, modular via structures that can be systematically implemented across multiple metal layers without proportionally increasing overall device complexity.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the electrical performance and reliability of the connections between the IC and flexible circuits, allowing for more efficient signal integrity and reduced resistance, thereby improving the functionality of proximity sensor devices and display devices.

Implementation Method 1

forming vias in a substrate of the IC die using a laser configured to drill the vias from the front side of the IC die

Methodology Applied
Scientific EffectLaser ablation: Laser Ablation

Implementation Method 2

forming metal contacts on first metal pads, and metal interconnects between second metal pads and the vias, using an single electroplating process

Methodology Applied
Scientific EffectElectroplating: Electroplating

Data Source

PatentUS10042488B2Through silicon vias for backside connection
Publication Date: 2018.08.07 SYNAPTICS INC

AI summary

In an example, a method of processing an integrated circuit (IC) die including active circuitry formed on a substrate and a front side having a plurality of metal layers formed on the substrate. The method includes forming vias in a substrate of the IC die using a laser configured to drill the vias from the front side of the IC die. The method includes forming metal contacts on first metal pads, and metal interconnects between second metal pads and the vias, using an single electroplating process, where the first metal pads and the second metal pads are exposed parts of a top layer of the plurality of metal layers, and where the metal interconnects at least partially fill the vias. The method includes thinning the substrate of the IC die to expose the metal interconnects in the vias at a back side of the IC die opposite the front side.