TSV Backside Interconnect Structure for Higher 3D IC Density
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Solution Overview
Problem
The semiconductor industry faces limitations in increasing circuit density due to physical constraints in two-dimensional (2D) IC formation, prompting the exploration of three-dimensional (3D) ICs through the use of through-substrate vias (TSVs) and backside interconnect structures.
Innovation Solution
The method involves forming TSVs in a semiconductor substrate, thinning the backside to expose the TSVs, and creating a concave or convex surface on the TSVs. An isolation film is formed, and a conductive layer is deposited, which includes portions replicating the surface topography of the TSVs. This structure enables efficient backside interconnects and redistribution lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If through-substrate vias (TSVs) and backside interconnect structures are used to form 3D ICs, then integration density and functionality are enhanced, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent transitions from 2D IC layout to 3D IC architecture by forming TSVs that extend vertically through the substrate and creating backside interconnect structures. This dimensional change allows circuit elements to be distributed across multiple layers (frontside and backside), significantly increasing integration density beyond what is achievable in planar 2D configurations.
Solution Approach 2:
The substrate is divided into multiple functional regions with TSVs segmented at different depths and locations. The backside interconnect structure is segmented into multiple conductive layers and isolation regions. This segmentation allows independent optimization of different circuit functions and simplifies the manufacturing process by breaking down complex 3D interconnections into manageable discrete elements.
2Adaptability or versatility
If TSVs are formed by etching vertical openings through substrate and filling with conductive material, then backside interconnects are enabled, but manufacturing precision requirements increase
Solution Approach 1:
The substrate is thinned and backside surface preparation is performed before TSV formation to establish precise geometric references. Isolation films are deposited and patterned in advance to define TSV locations and dimensions. These preliminary actions ensure that subsequent TSV etching and filling operations can be performed with high precision, enabling reliable backside interconnect formation.
3Reliability
If two dies are bonded together with wire bonds to carrier substrate, then electrical connections are formed, but carrier substrate size must be larger than dies
Solution Approach 1:
Instead of bonding dies to a large carrier substrate and making wire bonds from the carrier, the patent inverts the approach by forming TSVs directly through the substrate and creating interconnect structures on the backside of the substrate itself. This eliminates the need for a larger carrier substrate, as the substrate serves dual purposes: supporting frontside circuitry and providing backside interconnect pathways.
Solution Approach 2:
The substrate is designed to perform multiple functions: it serves as the mechanical support for frontside dies, provides vertical interconnect pathways through TSVs, and hosts backside interconnect structures. This multi-functionality eliminates the need for separate carrier substrates and wire bonds, reducing overall package size while maintaining reliable electrical connections between stacked dies.
Data Source
AI summary
A semiconductor device includes a through-substrate via extending from a frontside to a backside of a semiconductor substrate. The through-substrate via includes a concave or a convex portion adjacent to the backside of the semiconductor substrate. An isolation film is formed on the backside of the semiconductor substrate. A conductive layer includes a first portion formed on the concave or convex portion of the through substrate via and a second portion formed on the isolation film. A passivation layer partially covers the conductive layer.