TSV Backside Interconnects with Non-Planar Bumps for 3D Integration
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Solution Overview
Problem
The semiconductor industry faces limitations in increasing integration density and interconnection complexity in two-dimensional integrated circuits, leading to increased circuit RC delay and power consumption, which are addressed by adopting three-dimensional integrated circuits and through-silicon vias for connecting dies and providing grounding paths.
Innovation Solution
A method for forming backside interconnect structures connected to through-substrate vias (TSVs) is developed, involving the formation of conductive features on the front side of a semiconductor substrate, followed by wafer thinning, lithography, and electrochemical plating to create TSVs and backside connectors with non-planar bumps for improved connectivity and reduced interconnection complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If more devices are integrated into one chip to increase integration density, then the number of components increases, but the number and lengths of interconnections increase leading to increased circuit RC delay and power consumption
Solution Approach 1:
The patent transitions from two-dimensional planar interconnections to three-dimensional vertical interconnections using Through-Silicon Vias (TSVs). This dimensional change allows signals to travel vertically through the substrate rather than laterally across the surface, dramatically reducing interconnection length and associated power consumption while maintaining high integration density
2Productivity
If more devices are integrated into one chip, then integration density improves, but circuit RC delay increases due to increased interconnection lengths
Solution Approach 1:
By implementing vertical TSV interconnections, the patent reduces the physical path length that electrical signals must travel. The via structures provide direct vertical pathways through the substrate, eliminating the need for long lateral interconnect paths and thereby reducing RC delay while supporting higher integration densities
3Productivity
If TSVs are used to connect dies and provide grounding paths, then three-dimensional integration is achieved, but the complexity of backside interconnect structures increases
Solution Approach 1:
The patent divides the backside interconnect structure into functionally distinct segments: TSVs for vertical signal transmission, separate grounding paths for electrical reference, and dedicated pad structures for die attachment. This segmentation allows each component to be optimized independently, managing overall complexity while enabling 3D integration
4Productivity
If wafer thinning is performed to enable backside access for TSV formation, then three-dimensional integration becomes possible, but manufacturing precision requirements increase
Solution Approach 1:
The patent performs wafer thinning as a preliminary step before TSV formation and backside interconnect fabrication. By reducing the substrate thickness in advance, the patent enables subsequent processing steps to be performed with reduced precision requirements, as the thinner substrate is more manageable during via drilling and metal deposition processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the integration density and reduces interconnection complexity, improving the performance and efficiency of three-dimensional integrated circuits by enabling more efficient connectivity and grounding, thereby addressing the limitations of two-dimensional circuits.
Implementation Method 1
electrochemical plating to create TSVs and backside connectors
Data Source
AI summary
A device includes a substrate having a front side and a backside, a through-via extending from the backside to the front side of the substrate, and a conductive pad on the backside of the substrate and over the through-via. The conductive pad has a substantially planar top surface. A conductive bump has a non-planar top surface over the substantially planar top surface and aligned to the through-via. The conductive bump and the conductive pad are formed of a same material. No interface is formed between the conductive bump and the conductive pad.