TSV Backside Power Distribution for Reduced IR Droop
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Solution Overview
Problem
Existing semiconductor device designs face challenges in efficiently delivering power to the backside network due to high internal resistance droop, particularly in traditional builds where C4s feed large BEOL vias, which then lead to fine BEOL vias, MOL, and finally devices.
Innovation Solution
A TSV and backside power distribution structure is implemented, featuring a combination of thin and thick wiring layers, with optimized via connections through silicon layers and BEOL regions, enabling direct power delivery from the packaging substrate to the top die, utilizing nano TSVs and super vias to reduce IR droop.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If traditional C4 feeds large BEOL vias to deliver power, then power delivery path is established, but internal resistance droop increases
Solution Approach 1:
The patent introduces a vertical dimension to power delivery by implementing Through-Silicon-Vias (TSVs) that penetrate the silicon substrate, transforming the traditional planar power distribution into a three-dimensional architecture. This allows power to be delivered directly from the packaging substrate through the silicon layer to the device layer, significantly reducing the horizontal current path length and associated IR droop.
Solution Approach 2:
The patent introduces an intermediate thick wiring layer positioned between the packaging substrate and the device layer. This intermediate layer acts as a power distribution hub that receives power from the substrate through large vias and redistributes it to devices through optimized pathways, effectively mediating the power delivery process and reducing overall resistance.
2Power
If thick wiring layer is added for power distribution, then power delivery capability improves, but device layer positioning becomes more complex
Solution Approach 1:
The patent segments the wiring structure into distinct functional layers: a thin wiring layer for signal connections and a thick wiring layer for power distribution. This segmentation allows each layer to be optimized independently for its specific function, simplifying the design and fabrication process while maintaining overall system performance.
Solution Approach 2:
The patent applies local quality by creating a thick wiring layer specifically in regions where high current density is required for power distribution, while maintaining a thin wiring layer in regions dedicated to signal connections. This localized differentiation optimizes both power delivery capability and signal integrity without unnecessarily increasing overall structural complexity.
3Reliability
If multiple via connections are implemented, then connection reliability improves, but manufacturing process complexity increases
Solution Approach 1:
The patent merges the formation of multiple via connections into integrated process steps. The TSVs are formed through a unified etching and filling process that simultaneously creates multiple vertical interconnects, and the via connections are established in combination with the wiring layer formation, reducing the total number of discrete manufacturing steps.
Solution Approach 2:
The patent performs preliminary actions by pre-forming the TSV structures and thick wiring layer configurations before final device assembly. This allows complex via networks to be established in advance during wafer fabrication, simplifying subsequent packaging and assembly processes while ensuring connection reliability.
Data Source
AI summary
A semiconductor device includes an electronic circuit within a device layer; wherein the device layer is between a thin layer of wiring for signal connections having a first thickness and a thick layer of wiring for power having a second thickness, the second thickness being greater than the first thickness; a silicon layer above the device layer, the thin layer of wiring, and the thick layer of wiring; a first via connection from a top of the semiconductor device to the thin layer of wiring; a second via connection from the top of the semiconductor device to the thick layer of wiring; and a packaging substrate with a connection to the thick layer of wiring.