On-Chip Decoupling via TSV and BEOL Metal Layers
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Solution Overview
Problem
Integrated circuit (IC) architectures often face constraints in placing on-chip decoupling capacitance, leading to high impedance in routing conductors, which is undesirable for high-frequency switching power supplies, necessitating an improved interconnection scheme for IC power supply circuitry.
Innovation Solution
The use of through-silicon vias (TSVs) and back-end-of-line (BEOL) metal layers with separate ground and power routing paths to minimize parasitic impedance, allowing for effective decoupling of power supply noise by forming conductive paths from power supply circuitry to decoupling capacitance circuitry, utilizing redistribution layers (RDL) and back-side metal (BSM) layers to reduce inductance and enhance noise suppression.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If on-chip decoupling capacitance is placed using standard front-end process metal layers, then the routing is simple, but the impedance (resistance and inductance) becomes high
Solution Approach 1:
The patent transitions from planar routing in standard metal layers to three-dimensional routing using through-silicon vias (TSVs) that penetrate the substrate vertically. This dimensional change allows decoupling capacitance to be placed in back-end-of-line (BEOL) metal layers, creating shorter and lower-impedance paths between power supply and ground while maintaining manufacturing feasibility through established via and multi-layer metal processes.
2Adaptability or versatility
If decoupling capacitance is placed far from power supply circuitry to meet architectural constraints, then placement flexibility is improved, but the effective decoupling performance deteriorates due to high impedance
Solution Approach 1:
By utilizing vertical TSV interconnects and multiple BEOL metal layers, the patent enables decoupling capacitance to be placed in different spatial locations (including areas not directly adjacent to power supplies) while maintaining low impedance through the vertical via paths. This allows placement flexibility to meet architectural constraints without sacrificing decoupling effectiveness.
Solution Approach 2:
The patent introduces TSVs and BEOL metal layers as intermediary structures that bridge the power supply circuitry and decoupling capacitance. These intermediaries provide low-impedance conductive paths that overcome the distance separation required by architectural constraints, effectively coupling the power supply to the decoupling capacitance despite spatial separation.
3Ease of manufacture
If standard metal layer routing is used for power supply interconnection, then the fabrication process is simple, but parasitic inductance and resistance increase
Solution Approach 1:
The patent employs vertical TSV routing combined with multi-layer BEOL metal structures to create three-dimensional power supply interconnection paths. This dimensional transition reduces the physical length of current paths and minimizes loop areas, thereby reducing parasitic inductance and resistance while utilizing standard via and multi-layer metal fabrication processes.
Solution Approach 2:
The patent segments the power supply interconnection into multiple discrete components: TSVs for vertical penetration, BEOL metal layers for horizontal routing, and distributed decoupling capacitance. This segmentation allows optimization of each segment's impedance characteristics while maintaining overall fabrication simplicity through modular integration of standard process elements.
Data Source
AI summary
An integrated circuit device is disclosed. The integrated circuit device includes a semiconductor die fabricated by a front-end semiconductor process and having oppositely disposed planar surfaces. The semiconductor die is formed with semiconductor devices, power supply circuitry coupled to the semiconductor devices, decoupling capacitance circuitry, and through-vias. The through-vias include a first group of vias coupled to the power supply circuitry and a second group of vias coupled to the decoupling capacitance circuitry. Conductors are formed in a first metal layer disposed on the semiconductor die in accordance with a back-end semiconductor process. The conductors are configured to couple to the first and second groups of through-vias to establish conductive paths from the power supply circuitry to the decoupling capacitance circuitry.