Combined TSV and BEOL Isolation Deposition for Semiconductor Manufacturing
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Solution Overview
Problem
The existing process for 3D integration in semiconductor devices requires two separate deposition steps for TSV isolation and liner deposition, leading to decreased pre-metal dielectric thickness and increased non-uniformity across the wafer, as well as additional complexity and cost.
Innovation Solution
A method is developed to form both the TSV isolation layer and the transistor-to-BEOL isolation layer during a single deposition process, involving the formation of a TSV trench through a shallow trench isolation layer, deposition of an isolation layer, and subsequent filling with a conductive material, while reducing the number of CMP steps and inspection processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If two separate deposition steps are used for TSV isolation and liner deposition, then complete TSV liner coverage is achieved, but pre-metal dielectric thickness non-uniformity increases and process complexity increases
Solution Approach 1:
The patent combines the TSV isolation layer deposition and the transistor-to-BEOL isolation layer deposition into a single deposition step. This merging of two separate processes into one reduces process complexity and eliminates the need for intermediate steps, directly addressing the contradiction between manufacturing precision and device complexity.
Solution Approach 2:
The single deposition layer serves multiple functions: it acts as both the TSV isolation layer and the transistor-to-BEOL isolation layer. This multi-functionality approach allows one process to achieve what previously required two separate processes, reducing overall process complexity while maintaining the necessary isolation functions.
2Reliability
If 200 nm of TSV trench isolation oxide is deposited at 100% step coverage, then complete TSV liner coverage is achieved, but PMD thickness decreases and non-uniformity increases
Solution Approach 1:
By merging the TSV isolation and transistor-to-BEOL isolation into a single deposition, the patent achieves complete coverage in one step without requiring excessive oxide thickness. This single step deposition provides the necessary coverage while maintaining better PMD thickness uniformity compared to the traditional two-step approach.
3Ease of manufacture
If TSV liner is completely removed during CMP process, then TSV formation is achieved, but additional CMP steps and inspection processes are required
Solution Approach 1:
The patent extracts and eliminates the need for complete TSV liner removal during CMP by using a single deposition approach that integrates both isolation functions. This reduces the number of CMP steps and inspection processes required, thereby improving manufacturing efficiency while maintaining complete TSV formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces pre-metal dielectric thickness non-uniformity and overall cost by integrating TSV and BEOL isolation layers in a single step, minimizing CMP and inspection requirements, and enhancing the efficiency of the semiconductor manufacturing process.
Implementation Method 1
forming an isolation layer on sidewalls and a bottom surface of the TSV trench and over the gate stack, the STI layer, and the silicon substrate
Implementation Method 2
forming the TSV trench by deep reactive-ion etching (DRIE)
Implementation Method 3
annealing the conductive material at a temperature of 100° C. to 450° C.
Data Source
AI summary
A method of forming a TSV isolation layer and a transistor-to-BEOL isolation layer during a single deposition process and the resulting device are disclosed. Embodiments include providing a gate stack, with source/drain regions at opposite sides thereof, and an STI layer on a silicon substrate; forming a TSV trench, laterally separated from the gate stack, through the STI layer and the silicon substrate; forming an isolation layer on sidewalls and a bottom surface of the TSV trench and over the gate stack, the STI layer, and the silicon substrate; forming a TSV in the TSV trench; forming a dielectric cap over the isolation layer and the TSV; and forming a source/drain contact through the dielectric cap and the isolation layer down to the source/drain contract regions.