TSV Bridge Microelectronic Assembly for Dense Die Interconnects
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current advanced packaging technologies for high-performance computing face challenges in achieving high interconnect densities, reduced routing distances, and improved signal and power integrity without increasing manufacturing complexity and costs, particularly in heterogeneous integration for applications like supercomputing and autonomous driving.
Innovation Solution
The development of microelectronic assemblies with multiple layers of dies coupled by redistribution layers (RDLs), featuring conductive pathways and interconnects that electrically couple dies with varying thicknesses and surface areas, and a package substrate, allowing for increased interconnect density and flexibility in design without excessive manufacturing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If through-silicon via bridges are used to couple dies, then interconnect density is improved, but manufacturing complexity increases
Solution Approach 1:
The via bridge formation process is segmented into distinct stages: forming recesses in first substrates, bonding substrates together, and then forming via bridges in the recesses. This segmentation allows each step to be optimized independently, reducing overall manufacturing complexity while achieving high interconnect density through the integrated via bridge structures.
Solution Approach 2:
Recesses are formed in the first substrates before bonding occurs. This preliminary action prepares the substrate architecture in advance, enabling subsequent via bridge formation to proceed more efficiently and reducing the complexity of the overall manufacturing process while maintaining high interconnect density.
2Adaptability or versatility
If multiple layers of dies are coupled with varying thicknesses, then design flexibility is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent accommodates dies with locally varying thicknesses and surface areas in different layers. Each die can have customized thickness and surface area characteristics tailored to its specific functional requirements, while the bonding process and via bridge formation are designed to handle these local variations without compromising overall manufacturing precision.
3Adaptability or versatility
If heterogeneous integration is implemented for high-performance computing, then functionality is improved, but manufacturing complexity increases
Solution Approach 1:
The patent describes a universal bonding and via bridge formation process that can accommodate heterogeneous die combinations with different materials, thicknesses, and functionalities. This multi-functional approach allows the same manufacturing process to handle diverse die types (logic, memory, sensors, etc.) integrated in three-dimensional stacks, achieving high functionality without proportionally increasing manufacturing complexity.
Data Source
AI summary
Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first layer having first dies in a first insulating material; a second layer on the first layer, the second layer including second dies having a first thickness and third dies having a second thickness different than the first thickness, the second dies and the third dies in a second insulating material, wherein the second dies and third dies have a first surface and an opposing second surface, and wherein the first surfaces of the second and third dies have a combined surface area between 3,000 square millimeters (mm2) and 9,000 mm2; and a redistribution layer (RDL) between the first layer and the second layer, the RDL including conductive pathways, wherein the first dies are electrically coupled to the second dies and the third dies by the conductive pathways and by interconnects.