TSV Bridge Assembly with Top-Die-First Routing Density Gain
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Solution Overview
Problem
Current advanced packaging technologies face challenges in achieving high interconnect density, reduced routing distances, and improved signal and power integrity for high-performance computing applications, while also being cost-effective and less complex to manufacture.
Innovation Solution
The proposed microelectronic assembly includes multiple layers of dies coupled by redistribution layers (RDLs) with conductive pathways, where the dies have varying thicknesses and surface areas, and are electrically coupled through interconnects and RDLs, allowing for increased interconnect density and reduced routing distances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional packaging technologies are used, then manufacturing simplicity and cost-effectiveness are maintained, but interconnect density and routing distance are insufficient for high-performance computing
Solution Approach 1:
The patent inverts the conventional bottom-up assembly approach by using a top-die-first method where the thickest die is placed first on the carrier, followed by thinner dies. This inversion simplifies the manufacturing process by eliminating the need for complex thickness compensation mechanisms while achieving high interconnect density and improved signal integrity through the through-silicon via bridge structure
Solution Approach 2:
The patent transitions from planar interconnect architecture to three-dimensional through-silicon via bridges, adding the vertical dimension to interconnections. This dimensional change enables shorter routing distances and improved signal integrity while maintaining manufacturing feasibility through the top-die-first assembly approach
2Reliability
If interconnect density is increased and routing distances are reduced, then signal and power integrity improve, but manufacturing complexity and cost increase
Solution Approach 1:
By inverting the assembly sequence to place the thickest die first, the patent achieves high interconnect density with standard manufacturing processes, avoiding the need for costly custom equipment or complex process steps that would otherwise be required to achieve the same results
Solution Approach 2:
The through-silicon via bridges are formed as integral parts of the die structure during semiconductor fabrication, eliminating the need for separate, costly post-assembly interconnect formation processes. The structure serves multiple functions simultaneously: providing mechanical support, electrical interconnection, and thermal management pathways
3Productivity
If through-silicon via bridges are used, then interconnect density increases and routing distances reduce, but manufacturing process complexity increases
Solution Approach 1:
The inverted top-die-first assembly approach simplifies the overall manufacturing process by allowing standard pick-and-place equipment to be used without modification, while the through-silicon via bridges provide the high-density interconnection capability that would otherwise require complex manufacturing steps
Data Source
Figure 1
Figure 2A~2B
Figure 2C
AI summary
Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first layer having first dies in a first insulating material; a second layer on the first layer, the second layer including second dies having a first thickness and third dies having a second thickness different than the first thickness, the second dies and the third dies in a second insulating material, wherein the second dies and third dies have a first surface and an opposing second surface, and wherein the first surfaces of the second and third dies have a combined surface area between 3,000 square millimeters (mm2) and 9,000 mm2; and a redistribution layer (RDL) between the first layer and the second layer, the RDL including conductive pathways, wherein the first dies are electrically coupled to the second dies and the third dies by the conductive pathways and by interconnects.