Through Silicon Via Buffer Layer for Surface Roughness
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The through-silicon via technique faces issues with rough surfaces due to high depth/width ratios in etched vias, leading to degraded step coverage and efficiency of material layers, particularly the seed layer, which affects the electrical and thermal performance of the 3D stack ICs.
Innovation Solution
A buffer layer is introduced between the barrier and conductive layers, formed using Chemical Vapor Deposition (CVD) processes, to smooth the contact surface and enhance adhesivity, thereby reducing seed layer thickness and processing costs, and facilitating easier filling of the main conductive layer without voids.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If etching is used to form through-silicon vias with high depth/width ratio, then via connection is achieved, but the via surface becomes rough with scallop cross-sectional profile
Solution Approach 1:
A buffer layer is introduced as an intermediary between the barrier layer and the conductive seed layer. This buffer layer has a gradient composition transitioning from silicon-rich at the interface with the via wall to copper-rich at the interface with the seed layer, thereby mediating the transition from the rough via surface to the smooth conductive layer and eliminating the scallop profile effect.
Solution Approach 2:
The buffer layer's composition parameters are gradually changed from silicon-rich near the via wall to copper-rich near the seed layer interface. This compositional gradient allows the buffer layer to adapt to the rough via surface while providing a smooth interface for the conductive layer, effectively resolving the surface roughness issue without changing the etching process itself.
2Ease of manufacture
If rough via surface is accepted, then material layer step coverage efficiency is degraded
Solution Approach 1:
The buffer layer serves as a mediator that decouples the rough via surface from the conductive seed layer deposition process. By providing a progressively smoother interface through its gradient composition, it enables efficient step coverage and uniform material layer deposition without requiring the via surface itself to be smooth.
Solution Approach 2:
The buffer layer is a composite material with varying composition across its thickness, transitioning from silicon-rich to copper-rich. This composite structure combines the advantages of both materials: silicon affinity for the via wall and copper affinity for the seed layer, thereby improving overall deposition efficiency and step coverage.
3Manufacturing precision
If buffer layer is added between barrier layer and conductive layer, then surface smoothness and adhesivity are improved, but process complexity increases
Solution Approach 1:
Rather than adding a completely new material layer, the buffer layer utilizes parameter changes in composition (from silicon-rich to copper-rich) within a single continuous layer. This approach achieves the desired smooth interface and improved adhesivity while minimizing structural complexity compared to multiple discrete layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The buffer layer improves the smoothness of the contact surface between the conductive and buffer layers, enhances thermal resistance, reduces processing time and costs, and prevents thermal cracks, while ensuring better adhesivity and step coverage, leading to improved electrical and thermal performance of the through silicon via structure.
Implementation Method 1
A buffer layer is introduced between the barrier and conductive layers, formed using Chemical Vapor Deposition (CVD) processes
Implementation Method 2
the conductive layer is formed on the buffer layer and fills the recess
Data Source
AI summary
A through silicon via structure is located in a recess of a substrate. The through silicon via structure includes a barrier layer, a buffer layer and a conductive layer. The barrier layer covers a surface of the recess. The buffer layer covers the barrier layer. The conductive layer is located on the buffer layer and fills the recess, wherein the contact surface between the conductive layer and the buffer layer is smoother than the contact surface between the buffer layer and the barrier layer. Moreover, a through silicon via process forming said through silicon via structure is also provided.