Stacked Memory TSV Defect Repair via Selective I/O Buffer Activation
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Solution Overview
Problem
Manufacturing defects in through silicon vias (TSVs) of stacked semiconductor memory devices lead to reduced yield and communication disruptions between memory chips.
Innovation Solution
Incorporating I/O buffers within memory chips that can be selectively activated based on TSV defect states, with buffer control circuits using non-volatile memory devices like OTP or EEPROM to manage and reroute data and command bus mappings when TSV defects occur.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If TSVs are manufactured to connect memory chips in stacked semiconductor memory devices, then communication speed between chips is improved, but manufacturing defects occur reducing yield
Solution Approach 1:
The patent segments the communication path by introducing intermediate I/O buffers at each memory chip level. These buffers act as independent segments that can operate autonomously, allowing communication to continue through alternative paths when TSV defects occur, thereby maintaining yield while preserving high-speed communication capability.
Solution Approach 2:
I/O buffers are introduced as intermediary components between memory chips and TSVs. These buffers serve as mediators that can detect TSV defects and reroute signals through alternative TSVs, enabling the system to maintain communication functionality despite manufacturing defects in the high-speed TSV connections.
2Reliability
If I/O buffers are selectively activated based on TSV defect states, then manufacturing yield is improved, but device complexity increases
Solution Approach 1:
The system implements self-service through automatic defect detection and rerouting mechanisms. I/O buffers autonomously detect TSV defects and activate alternative buffers without external intervention, simplifying the overall control architecture while maintaining high yield through automated adaptability to manufacturing variations.
Solution Approach 2:
Multiple I/O buffers are pre-configured at each memory chip level before operation. This preliminary arrangement of redundant buffers enables immediate defect response without complex real-time control logic, as the system simply needs to switch between pre-positioned alternatives rather than dynamically generate rerouting solutions.
3Reliability
If redundant I/O buffers are implemented to bypass defective TSVs, then reliability is improved, but manufacturing cost increases
Solution Approach 1:
The patent implements partial redundancy by providing I/O buffers at each memory chip level rather than full system-wide redundancy. This partial action approach achieves sufficient reliability for bypassing defective TSVs while avoiding the excessive cost of complete redundancy, optimizing the trade-off between reliability and manufacturing cost.
Data Source
AI summary
A stacked semiconductor memory device according to the inventive concepts may include a plurality of memory chips stacked above a processor chip, a plurality of TSVs, and I/O buffers. The TSVs may pass through the memory chips and are connected to the processor chip. I/O buffers may be coupled between all or part of the memory chips and the TSVs and may be selectively activated on the basis of defective states of the TSVs.