TSV Bumping Pad Integration via Selective Dry Etching
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Solution Overview
Problem
Conventional methods for fabricating semiconductor devices with through silicon via (TSV) and bumping pads face challenges in improving integration density due to undercuts generated during wet etching processes, making it difficult to enhance the degree of integration.
Innovation Solution
The implementation of semiconductor devices with TSV structures and bumping pads formed using damascene processes, where TSVs pass through interlayer insulating layers and substrates, and bumping pads are formed with specific layers and materials to ensure electrical connectivity and integration, including the use of silicon carbonitride for the back-side blocking layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If wet etching process is used to remove pad barrier layer and pad seed layer, then the layers can be removed, but undercuts are generated which prevent improvement of integration density
Solution Approach 1:
The patent changes the etching parameters by switching from wet etching to selective dry etching processes. This parameter change allows precise removal of the pad barrier layer and pad seed layer without generating undercuts, thereby improving manufacturing precision and integration density while maintaining reliability
Solution Approach 2:
The patent replaces the wet etching chemical process with a selective dry etching process. This substitution eliminates the undercut formation issue associated with wet etching while achieving the same layer removal function, thus resolving the contradiction between manufacturing precision and reliability
2Productivity
If conventional bumping pad fabrication is used, then simple processes are employed, but integration density cannot be improved due to undercut generation
Solution Approach 1:
The patent changes the fabrication process parameters from conventional wet etching to selective dry etching with specific etch selectivities. This enables finer feature sizes and higher integration density while the added process steps are managed through systematic process integration
Solution Approach 2:
The patent segments the bumping pad fabrication into distinct stages: TSV formation, pad barrier layer deposition, pad seed layer deposition, and selective removal. This segmentation allows each step to be optimized independently, achieving high integration density while maintaining controllable process complexity
3Reliability
If TSV structure passes through substrate with protruding bottom end, then electrical connectivity is achieved, but reliable bumping pad formation is difficult due to undercut issues
Solution Approach 1:
The patent changes the etching selectivity parameters to enable precise control over the removal of pad barrier and seed layers. This allows the TSV structure with protruding bottom end to be properly formed and connected to bumping pads without undercut generation, achieving both reliable electrical connectivity and precise bumping pad formation
Solution Approach 2:
The patent introduces carefully controlled etching processes as intermediary steps between TSV formation and bumping pad creation. These intermediary selective removal steps precisely define the interface between the protruding TSV bottom end and the bumping pads, ensuring both electrical connectivity and formation precision
Data Source
AI summary
Semiconductor devices are provided. The semiconductor devices include a substrate, a first interlayer insulating layer disposed on a front-side of the substrate, a TSV structure passing through the first interlayer insulating layer and the substrate. The TSV structure has a bottom end protruding from a back-side of the substrate, a back-side insulating layer and a back-side passivation layer disposed on the back-side of the substrate, and a bumping pad buried in the back-side insulating layer and the back-side passivation layer and disposed on the bottom end of the TSV structure. The bottom end of the TSV structure protrudes into the back-side bumping pad, and top surfaces of the back-side passivation layer and the back-side bumping pad are coplanar.