TSV Dielectric Reliability Monitoring via Capacitive Test Structures

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Solution Overview

Problem

Current methods for testing and monitoring dielectric reliability in 3D integrated circuits with through-silicon vias (TSVs) are inadequate for detecting stress, strain, and damage that affect metallization continuity and interfacial integrity, particularly in the back-end-of-line (BEOL) stack and proximity accuracy.

Innovation Solution

A TSV test structure comprising multilevel capacitive test structures connected to a measurement circuit, where capacitance measurements are taken to derive a proximity effect factor, quantifying the impact of TSVs on adjacent dielectric regions, and used for monitoring and reliability testing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If traditional testing methods are used for TSV structures, then the testing process is simple, but the ability to detect stress, strain, and damage in the BEOL stack is insufficient

Engineering Contradiction:

Improvedetection capabilityVSAvoidtest structure complexity

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The test structure is segmented into multiple functional components: multilevel capacitive test structures for different metallization levels, reference structures, and measurement circuits. Each segment serves a specific purpose in detecting different aspects of dielectric reliability, enabling comprehensive stress and damage detection while maintaining systematic organization

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Capacitive test structures serve as intermediary elements between the TSV-induced stress fields and the measurement circuits. These intermediaries convert mechanical stress and strain effects into measurable electrical capacitance changes, enabling indirect but accurate detection of dielectric reliability issues without direct interference with the TSV operation

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If multilevel capacitive test structures are added to monitor dielectric reliability, then detection capability improves, but device complexity increases

Engineering Contradiction:

Improvedielectric reliability monitoringVSAvoidtest structure complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The multilevel capacitive test structures are designed to serve multiple functions simultaneously: monitoring stress, detecting strain, measuring dielectric integrity, and assessing metallization continuity across different metallization levels. This multi-functionality reduces the need for separate dedicated test structures for each parameter, thereby limiting the increase in overall device complexity

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The test structure employs a nested configuration where capacitive elements are integrated within and around the TSV structure across multiple metallization levels. The test structures are embedded in the BEOL stack, with capacitive plates positioned at different levels, creating a compact nested arrangement that monitors dielectric reliability without occupying excessive space or adding significant structural complexity

Inventive Principle:

Principle #7Nested doll (Nesting)

3Reliability

If comprehensive test structures are implemented, then reliability monitoring improves, but manufacturing complexity increases

Engineering Contradiction:

Improvemetallization continuity and interfacial integrityVSAvoidmanufacturing process complexity

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The capacitive test structures are formed during the standard backend-of-line (BEOL) fabrication process, before final packaging and testing. The test structures are integrated into the metallization stack during normal manufacturing steps, allowing preliminary formation of test elements without requiring separate post-fabrication processing stages. This preliminary integration reduces manufacturing complexity by utilizing existing process steps

Inventive Principle:

Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enables effective detection of abnormalities and stress in the BEOL stack, improving metallization continuity and interfacial integrity, and determining the range of influence of TSVs, enhancing the reliability and monitoring capabilities of 3D integrated circuits.

Implementation Method 1

measuring a first multilevel test structure's capacitance of a TSV test structure

Methodology Applied

Scientific EffectCapacitance: Capacitance

Data Source

PatentUS9404953B2Structures and methods for monitoring dielectric reliability with through-silicon vias

Publication Date: 2016.08.02 INTERNATIONAL BUSINESS MACHINE CORPORATION

AI summary

Embodiments of the present invention provide a variety of structures and method for detecting abnormalities in the back-end-of-line (BEOL) stack and BEOL structures located in close proximity to through-silicon vias (TSVs) in a 3D integrated chip. The detected abnormalities may include stress, strain, and damage that will affect metallization continuity, interfacial integrity within a metal level, proximity accuracy of the TSV placement, and interlevel dielectric integrity and metallization-to-TSV dielectric integrity. Additionally, these structures in conjunction with each other are capable of determining the range of influence of the TSV. That is, how close to the TSV that a BEOL line (or via) needs to be in order to be influenced by the TSV.