3D TSV Capacitor-Inductor Structure for Higher Functional Density
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Solution Overview
Problem
Current three-dimensional capacitors and inductors on silicon have low functional density and silicon utilization due to large area occupation and limited capacitance and inductance values, making them inadequate for high-density chip integration.
Innovation Solution
A three-dimensional capacitor-inductor structure using a high-functional-density through silicon via with a metal-insulating layer-metal configuration on the sidewall and center-filled metal within the via, combined with planar thick metal rewiring, to increase capacitance and inductance values and integrate components closer to the chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional through silicon via (TSV) is used as interconnect wire only, then the structure is simple to manufacture, but the functional density is low and silicon utilization rate is very low
Solution Approach 1:
The TSV structure is designed to perform multiple functions simultaneously: it serves as an interconnect wire for signal transmission, provides a substrate for forming three-dimensional capacitors on its sidewall, and contains center-filled metal for three-dimensional inductor construction. This multi-functional design resolves the contradiction by enabling high functional density while maintaining the simple TSV manufacturing process.
Solution Approach 2:
The invention nests multiple functional components within and around the TSV structure: the center-filled metal is nested inside the TSV hole, the three-dimensional capacitor is formed on the TSV sidewall, and the planar thick metal rewiring is integrated with the TSV. This nested configuration maximizes silicon utilization by packing multiple functions into a single vertical via structure.
2Ease of manufacture
If TSV occupies large area of silicon, then the structure is easy to form, but the functional density and silicon utilization rate are very low
Solution Approach 1:
The invention transitions from two-dimensional planar components to three-dimensional vertical structures. The TSV extends vertically through the silicon substrate, and functional components are arranged in three dimensions (center-filled metal inside, sidewall capacitor on exterior, planar rewiring at top/bottom). This vertical integration dramatically reduces the horizontal silicon area occupied while maintaining ease of formation through standard TSV processes.
Solution Approach 2:
By nesting multiple functional elements within the vertical TSV structure (center-filled metal inside the via, sidewall capacitor on the exterior surface), the invention maximizes the use of the vertical dimension, thereby reducing the horizontal footprint on silicon and improving functional density without complicating the basic TSV formation process.
3Device complexity
If discrete capacitors and inductors are used on PCB, then the design is simple, but the capacitance and inductance values are too small and quantities are insufficient
Solution Approach 1:
The invention merges previously discrete components (capacitors and inductors) with the TSV interconnect structure. The sidewall capacitor and center-filled metal inductor are integrated directly into the TSV, eliminating the need for separate discrete components on PCB. This integration maintains design simplicity while dramatically increasing capacitance and inductance values through three-dimensional geometry and closer proximity to active devices.
Solution Approach 2:
By transitioning from two-dimensional PCB mounting to three-dimensional integration within the TSV structure, the invention achieves much larger capacitance and inductance values in a compact footprint. The vertical arrangement and close proximity of conductive elements in three dimensions enable higher values without increasing overall device complexity.
Data Source
AI summary
The invention pertains to the technical field of semiconductor devices, and specifically relates to a three-dimensional capacitor-inductor based on a high-functional-density through silicon via structure and a manufacturing method, The three-dimensional capacitor-inductor of the present invention includes: a substrate formed with a through silicon via; a three-dimensional capacitor, formed on a sidewall of the through silicon via, and sequentially including a first metal layer, a second insulating layer; and a second metal layer; and a three-dimensional inductor, composed of center-filled metal of the through silicon via and planar thick metal rewiring, wherein a first insulating layer is provided between the sidewall of the through silicon via and the three-dimensional capacitor, and a third insulating layer is provided between the three-dimensional capacitor and the three-dimensional inductor, The invention can effectively increase the values of capacitance and inductance in an integrated system, and at the same time can integrate capacitors and inductors near the chip in three-dimensional integration, and can also improve the functional density of through silicon via in three-dimensional integration and increase the utilization rate of silicon in system integration. Compared with discrete capacitors and inductors on other organic substrates, the integration can be greatly improved.