TSV Capacitors for SRAM Single Event Upset Resistance
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Solution Overview
Problem
Integrated circuits, particularly SRAM cells, are increasingly susceptible to Single Event Upsets (SEUs) due to reduced critical charge and target area as technology scales, necessitating a solution that enhances SEU resistance without adding complexity or cost using standard CMOS processes.
Innovation Solution
The integration of Through Silicon Vias (TSVs) as capacitors coupled to the Q and Qbar nodes of memory cells increases the critical charge, reducing sensitivity to neutron and alpha particle-induced SEUs, thereby enhancing SEU resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If technology scaling is continued to reduce target area, then area is reduced, but critical charge decreases and SEU susceptibility increases
Solution Approach 1:
The patent embeds capacitive structures within the existing SRAM cell architecture by utilizing nested capacitor configurations that are integrated into the cross-coupled inverter structure. This nesting approach increases critical charge without significantly increasing the overall cell area, as the capacitive elements are incorporated within the existing layout boundaries rather than adding external structures.
Solution Approach 2:
The patent transitions from planar capacitance to three-dimensional capacitive structures by implementing vertical field effect transistors (VFETs) and stacked capacitor configurations. This dimensional change allows for increased capacitance values within the same footprint area, effectively increasing critical charge without proportionally increasing the target area, thus maintaining area efficiency while improving SEU resistance.
2Reliability
If special non-standard processes are used to maximize Qcrit, then critical charge increases and SEU resistance improves, but manufacturing complexity and cost increase
Solution Approach 1:
The patent designs capacitive structures that serve multiple functions: they provide the necessary capacitance for increased critical charge, act as part of the cross-coupled inverter logic, and can be integrated with existing CMOS fabrication processes. This multi-functionality eliminates the need for separate dedicated capacitor structures and special processing steps, thereby maintaining ease of manufacture while achieving improved SEU resistance.
Solution Approach 2:
The patent achieves increased critical charge by modifying existing process parameters within standard CMOS technology, such as adjusting capacitor dimensions, dielectric material properties, and transistor geometries, rather than introducing entirely new process steps. These parameter changes can be implemented using existing fabrication capabilities, avoiding the need for special non-standard processes and associated complexity.
3Reliability
If capacitance is increased to maximize Qcrit, then critical charge increases, but device area increases
Solution Approach 1:
The patent employs vertical field effect transistors (VFETs) and three-dimensional capacitor stacking to increase capacitance values without proportionally increasing planar area. By utilizing the vertical dimension for capacitive structures, the patent achieves higher critical charge while maintaining compact footprints, effectively decoupling the relationship between capacitance magnitude and lateral area occupation.
Solution Approach 2:
The patent integrates capacitive elements within the existing SRAM cell structure through nested configurations, where capacitor structures are embedded within or alongside the cross-coupled inverter transistors. This nesting allows the capacitive components to share space with logic elements, increasing effective capacitance without requiring additional dedicated area, thus maintaining high critical charge with minimal area penalty.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The use of TSVs as capacitors significantly increases the critical charge of memory cells, reducing SEU susceptibility and failure rates, while maintaining compatibility with standard CMOS technology and minimizing additional process steps or costs.
Implementation Method 1
By using one or more Through Silicon Vias (TSVs) as capacitor(s) coupled to the Q and/or Qbar nodes of the memory cell, the critical charge (Qcrit) of the circuit is increased
Implementation Method 2
The capacitors include a dielectric liner that isolates the TSV capacitor from the silicon substrate
Data Source
AI summary
Integrated circuits and methods for reducing the Single Event Upset (SEU) susceptibility of a memory cell are disclosed. By using one or more Through Silicon Vias (TSVs) as capacitor(s) coupled to the Q and/or Qbar nodes of the memory cell, the critical charge (Qcrit) of the circuit is increased. In so doing, the memory cell has greater resistance to an SEU occurrence and reduced sensitivity to neutron and alpha or other charged particle events. The capacitor(s) can be coupled between the Q or Qbar node(s) and a silicon substrate, or between the Q and Qbar nodes, for example.