TSV Cavity Structure for Lower Parasitic Capacitance
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Solution Overview
Problem
The existing semiconductor structures with through semiconductor vias (TSVs) face challenges in minimizing parasitic coupling capacitance, which increases delay and power consumption due to the interaction between TSV conductors and the semiconductor substrate.
Innovation Solution
Incorporating a cavity structure with a first cavity portion surrounding the middle section of the TSV and multiple second cavity portions surrounding the upper section, in direct contact with the TSV and semiconductor substrate, respectively, to reduce the parasitic coupling capacitance while maintaining structural integrity through semiconductor bridge portions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a through semiconductor via (TSV) is formed in a semiconductor substrate, then electrical connections between IC structures on both sides of the substrate are enabled, but parasitic coupling capacitance increases causing delay and power consumption
Solution Approach 1:
The patent extracts the harmful semiconductor substrate material from around the TSV by creating a cavity. The cavity removes the substrate that would otherwise form a parasitic capacitor with the TSV conductor, thereby eliminating the source of parasitic coupling capacitance while preserving the TSV's electrical connection function.
Solution Approach 2:
The patent introduces a dielectric liner as an intermediary material between the TSV conductor and the semiconductor substrate. This dielectric liner acts as a mediator that reduces the parasitic coupling capacitance by providing electrical isolation, allowing the TSV to maintain its electrical connection function while minimizing energy loss.
2Loss of energy
If a cavity is created around the TSV to reduce parasitic capacitance, then parasitic coupling capacitance is reduced, but structural integrity of the TSV may be compromised
Solution Approach 1:
The patent applies local quality by creating a cavity only in specific regions around the TSV while leaving other regions intact. The cavity is formed to surround portions of the TSV where parasitic capacitance is most problematic, while maintaining substrate support in areas where structural integrity is critical. This localized approach optimizes the balance between reducing parasitic capacitance and maintaining structural strength.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic capacitance by approximately 80% and relieves stress in the semiconductor substrate, while providing structural support and integrity to the TSVs.
Implementation Method 1
A parasitic coupling capacitance is formed by the TSV conductors and the semiconductor substrate with the dielectric liner therebetween. The parasitic coupling capacitance can increase delay and power consumption of the IC structures. It is a challenge to limit the parasitic coupling capacitance in this setting.
Implementation Method 2
the stress relief structure reduces stress in the semiconductor substrate
Data Source
AI summary
A structure includes a through semiconductor via (TSV) in a semiconductor substrate. The structure also includes a cavity including a first cavity portion in the semiconductor substrate and surrounding a middle section of the TSV and in direct contact with the TSV. The cavity also includes a plurality of second cavity portions in the semiconductor substrate and surrounding an upper section of the TSV. The semiconductor substrate is between adjacent second cavity portions, creating a bridge portion that provides structural support. The cavity reduces parasitic capacitance.