TSV Interconnect via Wafer Cavity for Stacked IC Reliability
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Solution Overview
Problem
Current methods for creating electrical connections between stacked IC devices through Through Semiconductor Vias (TSVs) face issues such as increased capacitance, resistance, and inductance due to additional interconnects, and risk of damage to metal contact pads during etching processes, especially when using direct oxide-to-oxide bonding techniques.
Innovation Solution
A method involving the creation of cavities in the bonding surfaces of IC devices before bonding, where a TSV opening is etched through the bonded assembly, forming an aggregate opening with the cavity, and a metal interconnection plug is produced within this opening to connect the IC devices, minimizing damage to contact pads and reducing the risk of overetching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If TSVs are etched after direct oxide-to-oxide bonding, then electrical connections between stacked wafers are achieved, but metal contact pads of the upper wafer become damaged due to overetching or sputtering
Solution Approach 1:
The cavity is formed in the upper wafer's bonding surface before bonding occurs. This preliminary action creates a protective recess that prevents the etching process from damaging the metal contact pads during TSV formation, while still allowing electrical connections to be established through the aggregate opening combining the TSV opening and cavity.
2Adaptability or versatility
If additional interconnects are applied after bonding and TSV formation, then external connections between wafers are provided, but capacitance, resistance and inductance of the interconnect structure increase
Solution Approach 1:
The invention extracts the harmful additional interconnect layer by using the cavity to directly expose the metal contact pad. This eliminates the need for separate via contacts and additional interconnect structures, thereby reducing capacitance, resistance, and inductance while maintaining external connection capability through the aggregate opening.
3Reliability
If landing pad on the bottom wafer is made larger to account for overlay tolerance, then bonding alignment is ensured, but via capture pad size increases and interconnect pitch is limited
Solution Approach 1:
The invention moves the alignment reference from the bonding pad area to the cavity position. By forming the cavity at a specific location on the upper wafer before bonding, the aggregate opening (TSV opening + cavity) provides precise alignment registration without requiring enlarged landing pads, thus maintaining small pad sizes and achieving finer interconnect pitch while ensuring bonding reliability.
Data Source
Figure 1a~1d
Figure 1e~1h
Figure 2a~2c
AI summary
The present invention is related to a method for bonding and interconnecting two or more IC devices (10a,10b) arranged on substrates such as silicon wafers (1a,1b), wherein the wafers are bonded by a direct bonding technique to form a wafer assembly, and wherein the multiple IC devices are provided with metal contact structures (4a,4b). At least the upper substrate is provided prior to bonding with a cavity (16) in its bonding surface. A TSV (Through Semiconductor Via) (18) is etched through the bonded wafer assembly and an aggregate opening (25,52) is formed comprising the TSV opening (18) and the cavity (16). After the formation of an isolation liner on at least part of the sidewalls of the aggregate opening (i.e. at least on the part where the liner isolates the aggregate opening from semiconductor material), a TSV interconnection plug is produced in the aggregate opening.