TSV Cavity Substrate for Fan-In Package-on-Package Interconnect
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Solution Overview
Problem
Conventional semiconductor device packages with stacked die require multiple substrates for electrical interconnections, increasing package thickness and degrading electrical performance due to longer signal propagation paths.
Innovation Solution
A method involving a substrate with a cavity and a conductive via, where a second substrate is disposed within the cavity, and a semiconductor die is electrically connected to the via, reducing the height and thickness of the semiconductor device by using through-silicon vias (TSVs) for direct interconnections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple substrates are used for electrical interconnections in stacked die packages, then electrical connections between die are achieved, but package thickness increases and signal propagation paths lengthen degrading electrical performance
Solution Approach 1:
The patent merges the functions of multiple substrates into a single substrate by implementing through-silicon via (TSV) technology. The TSVs provide vertical electrical interconnections through the substrate thickness, eliminating the need for multiple separate substrates while maintaining all necessary electrical connections between stacked die.
Solution Approach 2:
The patent transitions from horizontal signal routing through multiple substrates to vertical signal routing through TSVs. By changing the dimension of signal propagation from lateral (through substrate planes) to vertical (through substrate thickness), the patent reduces the overall package footprint and improves electrical performance.
2Reliability
If multiple substrates are used for electrical interconnections, then connections between stacked die are facilitated, but signal propagation paths lengthen degrading electrical performance
Solution Approach 1:
The patent combines multiple substrate functions into one unified substrate structure with integrated TSVs. This merging eliminates the cumulative signal path length that would result from passing through multiple separate substrates, thereby reducing overall signal propagation distance and improving electrical performance.
Solution Approach 2:
The TSVs act as intermediary conductive pathways that directly connect signal sources to destinations through the substrate. Instead of signals traveling through multiple substrate interfaces and lateral paths, the TSVs provide direct vertical conduits that mediate and shorten the signal propagation path.
3Device complexity
If conventional substrate stacking is used, then electrical interconnections are established, but device height and thickness increase
Solution Approach 1:
The patent consolidates multiple substrate layers into a single substrate with vertically integrated TSVs. This merging reduces the device thickness by eliminating the physical stacking of multiple substrates while maintaining all necessary interconnection functions through the vertical via structure.
Solution Approach 2:
The TSVs are nested within the substrate structure, with conductive materials filled within the via holes that are formed through the substrate. This nesting approach allows complex interconnection functionality to be embedded within the substrate itself rather than requiring additional external substrate layers.
Data Source
AI summary
A semiconductor device has a substrate with a cavity formed through first and second surfaces of the substrate. A conductive TSV is formed through a first semiconductor die, which is mounted in the cavity. The first semiconductor die may extend above the cavity. An encapsulant is deposited over the substrate and a first surface of the first semiconductor die. A portion of the encapsulant is removed from the first surface of the first semiconductor die to expose the conductive TSV. A second semiconductor die is mounted to the first surface of the first semiconductor die. The second semiconductor die is electrically connected to the conductive TSV. An interposer is disposed between the first semiconductor die and second semiconductor die. A third semiconductor die is mounted over a second surface of the first semiconductor die. A heat sink is formed over a surface of the third semiconductor die.