TSV Semiconductor Chip Insulation Stack for Wiring Pad Crack Resistance
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Solution Overview
Problem
Existing semiconductor packages face reliability issues due to stress concentration on wiring pads connected to through silicon vias (TSV) during temperature changes, leading to interface cracks with the insulation layer, especially when using insulation layers with low dielectric constants.
Innovation Solution
A semiconductor chip design that includes a substrate with a front wiring structure featuring a low dielectric constant first insulation layer and a high dielectric constant second insulation layer, where the wiring pad is positioned at the interface between the two layers, and a through via that penetrates the substrate and first insulation layer to connect the front and rear wiring structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a low dielectric constant insulation layer is used, then signal transmission performance is improved, but stress concentration and interface cracks occur during temperature changes
Solution Approach 1:
The patent employs a composite insulation structure consisting of a first insulation layer with low dielectric constant (e.g., porous silicon oxide, organosilicate glass) and a second insulation layer with high dielectric constant (e.g., silicon nitride, silicon oxide). This composite configuration allows the low-k first layer to provide excellent signal transmission performance while the high-k second layer provides high mechanical strength and stress resistance, thereby resolving the contradiction between signal performance and stress resistance.
Solution Approach 2:
The patent applies different material properties to different regions: the first insulation layer directly surrounding the wiring pad uses low dielectric constant material optimized for electrical performance, while the second insulation layer provides mechanical support and stress distribution. This localized optimization ensures that each layer performs its specific function effectively, preventing interface cracks while maintaining signal transmission quality.
2Reliability
If the wiring pad is directly connected to TSV, then electrical connection is achieved, but stress concentration occurs during temperature cycling
Solution Approach 1:
The patent introduces an intermediary structure consisting of multiple insulation layers between the wiring pad and the TSV connection. The first insulation layer with low dielectric constant provides electrical isolation and signal transmission, while the second insulation layer with high dielectric constant acts as a stress buffer. This intermediary configuration distributes the thermal stress that occurs during temperature cycling, preventing direct stress concentration on the wiring pad and improving temperature cycling resistance.
3Reliability
If a single insulation layer is used, then manufacturing process is simple, but stress distribution is poor leading to interface cracks
Solution Approach 1:
The patent implements a composite insulation layer structure with a first insulation layer having low dielectric constant and a second insulation layer having high dielectric constant. This composite structure improves stress distribution by combining materials with complementary properties: the low-k material provides electrical performance while the high-k material provides mechanical strength. Although the structure becomes more complex, the performance improvement in stress distribution and crack resistance justifies the added complexity.
Data Source
AI summary
A semiconductor chip includes a substrate; a front wiring structure on a front surface of the substrate and that includes a first insulation layer, a second insulation layer on the first insulation layer, a wiring pad, a first connection pad, and a plurality of first vias that electrically connect the wiring pad and the first connection pad; a rear wiring structure on a rear surface of the substrate and that includes a second connection pad; and a through via that penetrates the substrate and the first insulation layer and electrically connects the front wiring structure and the rear wiring structure. A dielectric constant of the first insulation layer is lower than a dielectric constant of the second insulation layer, the wiring pad is located at an interface of the first insulation layer and the second insulation layer, and the first connection pad is embedded in the second insulation layer.