TSV Interconnect Chip Packaging for Simpler Multi-Chip Routing
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Solution Overview
Problem
Existing multi-chip module technologies face challenges in efficiently interconnecting semiconductor chips due to complex fabrication processes and design restrictions, particularly in managing thermal expansion and signal transmission across different materials.
Innovation Solution
A semiconductor chip device with a first molding layer encasing an interconnect chip featuring a through substrate via (TSV) and conductive structures that facilitate vertical electrical coupling, allowing for easier access to both regions of semiconductor chips for power, ground, and signal transmission, and utilizing a redistribution layer (RDL) structure for efficient interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional multi-chip module technologies use complex fabrication processes with TSVs and RDL structures, then electrical interconnect capability is improved, but manufacturing complexity and design restrictions increase
Solution Approach 1:
The patent divides the interconnection system into separate functional components: the organic substrate provides mechanical support and routing, while TSVs provide vertical through-silicon vias for direct chip-to-substrate connections. This segmentation allows each component to be optimized independently, reducing overall manufacturing complexity while maintaining electrical interconnect capability.
Solution Approach 2:
The organic substrate acts as an intermediary between the semiconductor chips and the external environment. It provides a flexible platform that can accommodate different chip configurations and routing requirements without requiring complex integrated structures, thereby simplifying the manufacturing process while ensuring reliable electrical connections.
2Stability of the object's composition
If conventional packages use rigid substrates with fixed routing, then structural stability is improved, but adaptability to different chip configurations decreases
Solution Approach 1:
The patent changes the material parameter of the substrate from rigid inorganic materials to flexible organic materials. This parameter change allows the substrate to accommodate different chip configurations, sizes, and routing patterns while maintaining structural stability, thereby improving design flexibility without sacrificing mechanical integrity.
Solution Approach 2:
The patent uses composite material structures combining organic substrates with TSV technologies. The organic substrate provides flexibility and adaptability, while the TSVs provide stable vertical interconnect pathways. This composite approach enables the package to adapt to different chip configurations while maintaining structural stability and reliable electrical connections.
3Reliability
If through substrate vias are used to provide vertical pathways, then electrical signal transmission is improved, but manufacturing steps and process complexity increase
Solution Approach 1:
The patent segments the via formation process into TSV fabrication on the substrate side and corresponding via formation on the chip side, allowing independent optimization of each process. The TSVs are formed through the organic substrate using simplified techniques, and the chip vias are formed separately, reducing overall process complexity while maintaining efficient vertical signal transmission pathways.
Data Source
AI summary
An embodiment of a semiconductor chip device can include a molding layer having a first side and a second side, an interconnect chip at least partially encased in the molding layer, the interconnect chip comprising a through substrate via (TSV) that extends through the interconnect chip, an insulating layer positioned on the first side of the molding layer, and a conductive structure that is positioned vertically below the interconnect chip and extends through the insulating layer, wherein the conductive structure is electrically coupled to the TSV.