TSV Semiconductor Chip Layout for CTE Warpage Compensation
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Solution Overview
Problem
The challenge of warpage in semiconductor chips due to the difference in coefficient of thermal expansion (CTE) between the wafer and metal layers during the manufacturing process of through silicon vias is not adequately addressed in existing technologies, affecting the stacking reliability of semiconductor packages.
Innovation Solution
Incorporating a lower metal layer on the semiconductor substrate with a higher CTE than the substrate material, shaped to minimize thermal expansion imbalance, thereby reducing warpage and enhancing manufacturing yield and assembly reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a metal layer is arranged on the wafer for redistribution, then electrical connectivity and signal routing are improved, but warpage occurs due to the difference in coefficient of thermal expansion (CTE) between the wafer and metal layer
Solution Approach 1:
The patent applies local quality by positioning the lower metal layer specifically in the peripheral region of the wafer, rather than uniformly across the entire surface. This localized placement targets the areas where CTE mismatch causes the most significant warpage, allowing the metal layer to provide CTE compensation where needed while maintaining electrical connectivity functions in the central region.
Solution Approach 2:
The patent changes the physical parameters of the metal layer by selecting materials with specific CTE values that match or compensate for the wafer's CTE. By carefully selecting the CTE parameter of the lower metal layer material and controlling its thickness, the patent achieves CTE compensation that reduces warpage while maintaining the necessary electrical properties.
2Productivity
If through silicon vias are used to achieve high integration and miniaturization, then stacking density and capacity are improved, but manufacturing complexity and warpage control difficulty increase
Solution Approach 1:
The patent applies preliminary action by forming the lower metal layer on the wafer before the warpage problem becomes critical during subsequent processing steps. This pre-established CTE compensation structure helps maintain wafer flatness throughout the TSV formation process, including etching, filling, and planarization steps, thereby simplifying overall manufacturing complexity while enabling high stacking density.
3Shape
If the lower metal layer is positioned on the periphery of the lower bump area, then CTE mismatch and warpage are reduced, but the area available for bump formation is reduced
Solution Approach 1:
The patent resolves this contradiction by applying local quality - placing the lower metal layer specifically in the peripheral region where it is most needed for CTE compensation, while leaving the central bump formation areas clear. This spatial differentiation allows the metal layer to perform its warpage control function without interfering with bump formation in the central region.
Solution Approach 2:
The patent segments the wafer surface into distinct functional zones: a peripheral region for CTE compensation (where the lower metal layer is placed) and a central region for bump formation. This segmentation allows each zone to optimize its specific function without compromising the other, maintaining both warpage control and sufficient bump formation area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively alleviates warpage, improving the manufacturing yield and assembly reliability of semiconductor chips and packages by stabilizing the structure under thermal stress.
Implementation Method 1
warpage may occur due to the difference in coefficient of thermal expansion (CTE) between a wafer and a metal layer arranged on the wafer for redistribution
Data Source
AI summary
A semiconductor chip may include: a semiconductor substrate; a through silicon via that vertically penetrates the semiconductor substrate; an integrated device layer on a first surface of the semiconductor substrate and including integrated devices; a multi-wiring layer on the integrated device layer and including layers of wires; an upper metal layer on the multi-wiring layer and connected to the wires; and a lower metal layer on a second surface of the semiconductor substrate. The semiconductor substrate may include a lower bump area on the second surface of the semiconductor substrate, the lower bump area including bump pads thereon, and the lower metal layer may be on a periphery of the lower bump area.