Through-Substrate Vias in CMOS Image Sensors for 3D Integration
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Solution Overview
Problem
The semiconductor industry faces limitations in increasing integration density and interconnection complexity in two-dimensional integrated circuits, leading to increased circuit RC delay and power consumption, which are addressed by transitioning to three-dimensional integrated circuits and stacked dies using Through-Silicon Vias (TSVs).
Innovation Solution
A process for forming Through-Substrate Vias (TSVs) in CMOS Image Sensor (CIS) chips, involving the formation of TSV openings, filling with metallic material, and creating Redistribution Lines (RDLs) to connect devices, along with a polymer layer for protection and interconnects, enabling efficient electrical coupling and reduced complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If more devices are integrated into one chip to increase integration density, then the number of components increases, but the number and length of interconnections increase, leading to increased circuit RC delay and power consumption
Solution Approach 1:
The patent transitions from two-dimensional planar interconnections to three-dimensional vertical interconnections using Through-Silicon Vias (TSVs). This dimensional change allows signals to travel vertically through the substrate rather than horizontally across the chip, significantly reducing interconnection length and associated power consumption while maintaining high integration density
2Productivity
If more devices are integrated into one chip to increase integration density, then the number of components increases, but the interconnection length increases, leading to increased circuit RC delay
Solution Approach 1:
The patent implements vertical Through-Silicon Vias (TSVs) that penetrate the substrate to create short direct pathways between front-side and back-side interconnect layers. This three-dimensional routing dramatically reduces signal path length compared to traditional planar routing, thereby reducing RC delay and enabling higher integration density without compromising signal speed
3Productivity
If Through-Silicon Vias are used to connect dies in stacked configurations, then integration density increases, but the manufacturing process complexity increases
Solution Approach 1:
The patent forms Through-Silicon Vias (TSVs) and back-side interconnect structures before stacking the dies. This preliminary formation of vertical interconnections and grounding paths enables subsequent stacking operations to proceed more efficiently, reducing overall manufacturing complexity compared to forming all interconnections after stacking
4Use of energy by moving object
If Through-Silicon Vias are used to provide grounding paths in stacked dies, then power consumption decreases, but the manufacturing process complexity increases
Solution Approach 1:
The patent implements Through-Silicon Vias (TSVs) that simultaneously serve multiple functions: providing vertical signal interconnections between stacked dies and establishing low-impedance grounding paths. This multi-functionality reduces power consumption through improved grounding while the TSV formation process is integrated into the existing stacking manufacturing flow, minimizing additional process complexity
Data Source
AI summary
A device includes a semiconductor substrate, an image sensor at a front surface of the semiconductor substrate, and a plurality of dielectric layers over the image sensor. A color filter and a micro lens are disposed over the plurality of dielectric layers and aligned to the image sensor. A through via penetrates through the semiconductor substrate. A Redistribution Line (RDL) is disposed over the plurality of dielectric layers, wherein the RDL is electrically coupled to the through via. A polymer layer covers the RDL.