TSV Chip Bonding Structure for Uniform CMP Pattern Density
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Solution Overview
Problem
Chemical mechanical polishing (CMP) techniques face challenges in achieving uniformity and post-CMP flatness due to varying pattern densities, particularly in through-silicon vias (TSVs) with high metal density, leading to unsatisfactory wafer surface flatness.
Innovation Solution
A method involving the formation of dummy holes and a protective layer to create a uniform pattern density, combined with a CMP process that includes forming TSVs and a second metal layer, ensuring uniformity and increased flatness without additional processes or costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If CMP process is applied to wafers with TSVs and varying metal densities, then wafer surface planarization is achieved, but post-CMP wafer surface flatness deteriorates due to different CMP rates in regions with different pattern densities
Solution Approach 1:
The patent introduces dummy holes in regions with low metal density to create uniform pattern density across the wafer surface. This local modification ensures that all regions, whether originally high-density or low-density, have consistent CMP rates, thereby achieving uniform wafer surface flatness after polishing
Solution Approach 2:
The patent modifies the pattern density parameter by adding dummy holes to change the metal distribution uniformity. This parameter change transforms the non-uniform CMP rates into uniform CMP rates across different wafer regions, resolving the flatness issue
2Reliability
If dummy holes are added to uniformize pattern density, then CMP uniformity improves, but device structure complexity increases
Solution Approach 1:
The patent combines the formation of dummy holes with the existing patterned insulating layer structure. The dummy holes are integrated into the same insulating layer that contains the functional holes, thereby achieving CMP uniformity without adding separate structural layers or complex multi-step processes
3Manufacturing precision
If additional processes are used to form dummy metal layer, then pattern density uniformity improves, but manufacturing cost and process complexity increase
Solution Approach 1:
The patent performs the dummy hole formation preliminarily during the TSV process, specifically utilizing the etching step that already creates openings in the patterned insulating layer. By preliminary establishing the dummy holes alongside functional holes, the patent achieves pattern density uniformity without requiring separate additional manufacturing processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enhances CMP uniformity and post-CMP flatness by maintaining uniform pattern density across the wafer surface, improving the yield and reducing deformation, while being compatible with TSV processes.
Implementation Method 1
CMP typically relies on chemical corrosion of a polishing slurry and abrasion of ultrafine particles to form a smooth and flat surface
Implementation Method 2
CMP typically relies on chemical corrosion of a polishing slurry and abrasion of ultrafine particles to form a smooth and flat surface
Data Source
AI summary
A method of manufacturing a semiconductor device includes: providing bonded first and second wafers; forming a patterned insulating layer on the second substrate, the patterned insulating layer having first holes and dummy holes both exposing the second substrate; forming a protective layer, which fills a partial depth of the dummy holes and covers side surfaces of the first holes; forming through-silicon vias (TSVs); and forming a second metal layer including an interconnect metal layer and a dummy metal layer, the interconnect metal layer filling the TSVs and electrically connected to the first metal layer, the dummy metal layer filling the dummy holes. The formation of the dummy metal layer is integrated in the TSV process and is therefore done without using any additional process or adding additional cost to enable uniform pattern density (e.g., metal density) across the surface of the second wafer and enhanced CMP uniformity.