3D Vertical Interconnects Using TSV Conductive Rings
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Solution Overview
Problem
The challenge in three-dimensional vertically interconnected stacks is to enhance the strength of electric interconnection and bonding between adjacent layers of chips while managing heat dissipation and signal interference, which is exacerbated by the scaling down of micro-solder balls or bonding pads and the increase in stacked layers, leading to reliability issues and performance degradation.
Innovation Solution
A three-dimensional vertically interconnected structure is proposed, featuring stacked chips with adhesive material, electrical and thermal conductive rings, and micro-fluid channels, along with a method that includes lithography, electroplating, and redistribution layers to form conductive poles and rings for reliable interconnections and heat management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If micro-solder balls or bonding pads are scaled down to maintain technological advantages, then packaging density and signal path length are improved, but electrical interconnection strength and bonding reliability deteriorate
Solution Approach 1:
The patent transitions from two-dimensional planar bonding (micro-solder balls/bonding pads on chip surfaces) to three-dimensional vertical bonding through TSV holes. By moving the bonding interface into the vertical dimension, the system achieves both high packaging density through compact stacking and reliable electrical interconnection through the robust TSV-bonding pad structure that extends through the substrate thickness.
Solution Approach 2:
The bonding pads are nested within the TSV hole structure, with the bonding pad forming the bottom surface of the TSV hole and the micro-solder ball positioned at the opening. This nested configuration allows the bonding interface to be integrated within the interconnection structure itself, achieving both space efficiency and mechanical strength.
2Productivity
If multiple bonding and reflow processes are performed to implement multi-layered stacks, then the number of stacked layers is increased, but damage to already bonded micro-solder balls or bonding pads increases
Solution Approach 1:
The bonding pads are pre-formed at the bottom of TSV holes before stacking, and the TSV structure itself serves as the bonding interface. This preliminary preparation of robust bonding structures allows subsequent stacking and reflow processes to proceed without damaging previously bonded joints, as the TSV-bonding pad configuration provides mechanical strength that withstands thermal cycling.
3Volume of moving object
If chip thickness is reduced to shorten signal path and enhance package density, then packaging density and signal path length are improved, but signal transmission interference between adjacent chips increases
Solution Approach 1:
The patent applies different functional qualities to different regions: the TSV holes provide localized electrical interconnection and shielding, while the dielectric material filling the TSV holes provides localized electromagnetic shielding. This localized quality enhancement at critical interconnection points reduces signal crosstalk between adjacent chips despite reduced spacing.
Solution Approach 2:
The dielectric material filling the TSV holes acts as an intermediary that provides electromagnetic shielding between adjacent signal paths. This intermediary substance prevents direct electromagnetic coupling between signals in vertically stacked chips, reducing crosstalk while allowing the chips to be positioned close together for high density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution provides flexible and reliable electric interconnections, effective heat dissipation, and reduced signal crosstalk, simplifying the fabrication process and increasing the yield of electroplated products by using organic materials and metallic solders for adhesion and conductive rings for interconnections.
Implementation Method 1
a first through layers of chips hole located at the inner of the first conductive ring on each layer
Data Source
AI summary
The present invention discloses a three-dimensional vertically interconnected structure and a fabricating method therefor. The structure comprises at least two layers of chips which are stacked in sequence or stacked together face to face. An adhesive material is used for adhesion between adjacent layers of the chips while each layer of the chips contains a substrate layer and a dielectric layer from bottom to top. A front surface of the chip has a first concave, which is filled with metal to form a first electrical conductive ring that connects to microelectronic devices inside the chip via a redistribution layer. A first through layers of chips hole with a first micro electrical conductive pole inside, penetrates the stacked chips. The structure in the present invention enhances the electric interconnection and the bonding between adjacent layers of chips while the instant fabricating method simplifies the process and increases the yield.