3D Configurable Logic via TSV and Segmented Masks
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Solution Overview
Problem
The increasing cost of mask sets for semiconductor manufacturing, particularly for custom Integrated Circuits, and the limitations of existing FPGA technologies in terms of flexibility, silicon area usage, and re-programmability, pose challenges for achieving high-density and cost-effective production of configurable logic devices.
Innovation Solution
The use of antifuse configurable interconnect circuits with transistors fabricated above or below the antifuse layers, combined with Through-Silicon-Via (TSV) technology, allows for a more efficient use of silicon area and reduced mask set costs by enabling the construction of configurable logic devices with improved vertical connectivity and modular architecture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional mask set methods are used for custom IC fabrication, then manufacturing precision is maintained, but mask set cost increases exponentially
Solution Approach 1:
The patent segments the IC fabrication process into two distinct parts: generic layers that can be reused across multiple products, and custom layers that are specific to each design. This segmentation allows the expensive mask set costs to be amortized across multiple products for the generic portions, while only paying for custom masks where necessary, thereby reducing overall mask set costs while maintaining fabrication precision through standardized processes for the generic layers.
Solution Approach 2:
The patent applies preliminary action by pre-fabricating generic layers that can be reused across multiple custom IC products. These pre-made layers are stored and can be applied to different custom designs without requiring new mask sets, thus reducing mask set costs while maintaining manufacturing precision through established fabrication processes.
2Adaptability or versatility
If FPGA technologies are used for configurable logic, then re-programmability is achieved, but silicon area usage increases
Solution Approach 1:
The patent moves from traditional 2D planar FPGA architectures to a 3D vertical architecture using Through-Silicon-Via (TSV) technology. By stacking logic layers vertically and connecting them through TSVs, the patent achieves high re-programmability through configurable interconnects while significantly improving silicon area utilization compared to conventional 2D FPGAs.
Solution Approach 2:
The patent creates a universal configurable logic platform where the same TSV-based 3D structure can be programmed to perform multiple different logic functions. The configurable interconnect layers allow a single physical device to be re-programmed for various applications, achieving multi-functionality without requiring separate dedicated hardware for each function, thus reducing overall silicon area usage.
3Adaptability or versatility
If custom layers are added for each custom product, then device functionality is customized, but mask set cost increases
Solution Approach 1:
The patent segments the device structure into reusable generic layers and customizable layers. The generic layers contain standard functions and interconnects that can be shared across multiple products, while only the necessary custom layers are fabricated with product-specific masks. This segmentation enables device customization without requiring complete custom mask sets for each product, thereby reducing mask set costs.
Solution Approach 2:
The patent merges multiple generic layers that can be reused across different custom products into a shared fabrication process. By combining these reusable layers with minimal custom layers, the patent achieves device customization while amortizing the mask set costs across multiple products, reducing the overall manufacturing cost.
4Device complexity
If Through-Silicon-Via technology is used, then vertical connectivity is enhanced, but device complexity increases
Solution Approach 1:
The patent introduces TSV technology to add a vertical dimension to IC interconnectivity, enabling connections between stacked layers through the silicon substrate. While this enhances vertical connectivity, the patent manages the associated fabrication complexity by integrating TSV formation into the standard CMOS fabrication process flow and by using automated alignment and etching techniques.
Data Source
AI summary
A method for developing a custom device, the method including: programming a programmable device, where the programmable device includes a layer of monocrystalline first transistors and alignment marks, the first layer of monocrystalline first transistors is overlaid by interconnection layers, the interconnection layers are overlaid by a second layer of monocrystalline second transistors, where the interconnection layers include copper or aluminum, where the programming includes use of the second transistors, where the programming includes use of N type transistors and P type transistors, and where the programmable device includes at least one programmable connection; and then a step of producing a volume device according to a specific programmed design of the programmable device, where the volume device includes the at least one programmable connection replaced with a lithography defined connection, and where the volume device does not have the second layer.