3D IC Connecting Via Structure for TSV Reliability
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Solution Overview
Problem
Existing methods for connecting through silicon vias (TSV) with conductive layers in integrated circuits face challenges in ensuring a robust connection due to stress-induced voids, which can be attributed to the limited contact area between the connecting via and the TSV.
Innovation Solution
A connecting via structure comprising a series of intersecting via bars is formed to increase the contact area between the conductive layer and the TSV, specifically using a 'bar net' or 'bar-line' pattern to reduce stress-induced voids, thereby enhancing the electrical connection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a traditional connecting via structure is used, then the device complexity is low, but the contact area between the connecting via and TSV is limited, resulting in stress-induced voids and reduced connection reliability
Solution Approach 1:
The connecting via structure is segmented into multiple individual via bars arranged in a grid pattern, rather than using a single solid via. This segmentation increases the total contact area with the TSV while maintaining manufacturability through standard lithography and plating processes. The multiple discrete via bars reduce stress concentration and prevent void formation compared to a single large via.
Solution Approach 2:
The connecting via structure transitions from a single-point or single-area contact to a two-dimensional grid array of via bars. This dimensional expansion across the TSV contact surface significantly increases the total contact area, distributing mechanical stress more evenly and eliminating the stress-induced voids that plague traditional single-via connections.
2Reliability
If the contact area between connecting via and TSV is increased, then stress-induced voids are reduced, but the manufacturing process becomes more complex
Solution Approach 1:
The via grid pattern uses a density of via bars that exceeds what would be needed for minimal connectivity, creating excessive contact area that guarantees robust mechanical and electrical connection. This over-engineering of the contact area ensures stress distribution well beyond the minimum required, preventing voids while remaining compatible with standard manufacturing capabilities.
Solution Approach 2:
The via structure parameters (number of via bars, spacing, dimensions) are optimized to achieve the desired contact area and stress distribution. By adjusting these parameters, the design achieves robust connections using conventional manufacturing processes, balancing manufacturing ease with connection reliability.
3Reliability
If a larger contact area is used to reduce stress-induced voids, then the electrical connection reliability improves, but the area consumed on the substrate increases
Solution Approach 1:
Segmenting the contact area into multiple small via bars distributed in a grid pattern achieves a large total contact area without requiring a large footprint. The segmented approach allows the contact area to be distributed efficiently across the available substrate space, maximizing contact area within minimal bounding box dimensions.
Solution Approach 2:
The contact area is expanded from a single large area or linear arrangement into a two-dimensional grid array. This dimensional reorganization packs the total contact area into a compact footprint, achieving large contact area without proportionally increasing the substrate area consumed, as the via bars are distributed efficiently in both x and y directions.
Data Source
AI summary
A method of forming an integrated circuit device includes providing a substrate including an active device, forming a through silicon via into the substrate, forming a device contact to the active device, forming a conductive layer over the through silicon via and the device contact, and forming a connecting via structure for electrically connecting the conductive layer with the through silicon via. An integrated circuit device includes a through silicon via formed into a substrate silicon material, a conductive layer formed over the through silicon via, and a connecting via structure formed between the conductive layer and the through silicon via for electrically connecting the conductive layer with the through silicon via. The connecting via structure comprises a first series of via bars intersected with a second series of via bars.