TSV Copper Plating in CMOS via Selective Etch
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Solution Overview
Problem
Conventional methods for forming through-substrate-vias (TSVs) in CMOS semiconductor devices face challenges due to incompatibility between TSV plating chemistry and metallization layers, particularly when etching through backend layers that expose metal layers like aluminum, which can be incompatible with the electroplating process.
Innovation Solution
A modified etch and electroplating process is used to form and fill TSV openings by exposing an underlying barrier layer, such as Ti/TiN, and filling with copper through electroplating, allowing for the integration of TSV interconnects into CMOS structures with metallization layers that are otherwise incompatible with standard plating chemistry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional etching is used to form TSV opening on CMOS device, then the TSV opening can be formed through backend layers, but the exposed metal layer (aluminum) is incompatible with electroplating chemistry
Solution Approach 1:
The patent applies preliminary action by performing a selective etch process before electroplating to remove the incompatible aluminum metal layer and expose the underlying TiN barrier layer. This preparatory step ensures that the surface is chemically compatible with the subsequent electroplating process, preventing plating defects and ensuring reliable copper deposition.
Solution Approach 2:
The patent extracts the problematic aluminum metal layer from the TSV opening by selective etching, removing only the incompatible material while preserving the underlying TiN barrier layer. This extraction eliminates the chemical incompatibility between aluminum and electroplating chemistry, allowing successful copper filling.
2Manufacturing precision
If BOX etch is used to stop on TiN layer, then TSV opening can be formed with proper landing, but oxide versus TiN selectivity is poor
Solution Approach 1:
The patent applies local quality by using a selective etch process that targets specific materials (aluminum and oxide) with different etch rates and selectivities. The process is designed to etch through oxide layers with high selectivity while stopping precisely on the TiN barrier layer, creating locally optimized etching conditions for each material layer encountered in the TSV path.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the successful formation of copper TSV interconnects in CMOS devices, overcoming the limitations of conventional methods and facilitating 3D packaging applications like interposers, wafer-level packaging, and system-in-package (SiP) and package-on-package (PoP) configurations.
Implementation Method 1
filling of the vias by copper electrodeposition
Data Source
AI summary
A semiconductor device composed of a through-substrate-via (TSV) interconnect, and methods for forming the interconnect.