Through Silicon Via Coupling Features for IC Packaging Alignment

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Solution Overview

Problem

The challenge is to develop an integrated circuit packaging system that achieves higher density, lower cost, and improved performance while addressing the miniaturization and integration needs of portable electronic devices, as existing technologies fail to fully meet these requirements.

Innovation Solution

The system involves a wafer substrate with a through silicon via and coupling features, where a first coupling feature extends from the top side and a second coupling feature is formed on the opposite side, enabling enhanced electrical connectivity and interlocking structures for improved joint strength and reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If integrated circuits are stacked into a single package to increase density, then packaging density is improved, but manufacturing complexity and alignment precision requirements worsen

Engineering Contradiction:
Improvepackaging densityVSAvoidalignment precision
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

The coupling features are designed to be self-aligning, where the protrusion and recess automatically find their correct relative positions during the stacking process, eliminating the need for high-precision external alignment equipment and procedures

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The coupling features utilize asymmetric geometry with a protrusion on one chip and a corresponding recess on the other chip, creating a unique fit that ensures correct orientation and position without requiring complex alignment mechanisms

Inventive Principle:
Principle #4Asymmetry

2Length of moving object

If miniaturization is pursued to reduce device size, then device dimensions are reduced, but solder joint reliability and structural strength worsen

Engineering Contradiction:
Improvedevice dimensionsVSAvoidsolder joint reliability
Core Design Contradiction:
Length of moving objectVSReliability

Solution Approach 1:

The coupling features extend vertically from the through-silicon via structure, adding height in the z-dimension to create larger effective bonding surfaces and mechanical interlocking geometry, compensating for the reduced lateral dimensions in miniaturized devices

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The coupling features incorporate curved or rounded geometries that provide mechanical interlocking and stress distribution, enhancing joint strength and reliability in miniaturized structures where straight angular features would be too fragile

Inventive Principle:
Principle #14Spheroidality (Curvature)

3Adaptability or versatility

If integration of more functions is pursued, then functional density is improved, but manufacturing cost and process complexity worsen

Engineering Contradiction:
Improvefunctional integrationVSAvoidmanufacturing cost
Core Design Contradiction:
Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The coupling features serve multiple functions simultaneously: providing mechanical support, enabling electrical connectivity through the through-silicon via, ensuring precise alignment, and creating mechanical interlocking - all within a single structural element, eliminating the need for separate components

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The coupling features merge the electrical via structure with mechanical coupling functionality, combining what would traditionally be separate elements (electrical connection and mechanical attachment) into a single integrated structure that simplifies manufacturing

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS8710670B2Integrated circuit packaging system with coupling features and method of manufacture thereof
Publication Date: 2014.04.29 JCET SEMICON (SHAOXING) CO LTD
  • US8710670B2 patent drawing
  • US8710670B2 patent drawing
  • US8710670B2 patent drawing

AI summary

A method of manufacture of an integrated circuit packaging system includes: providing a wafer substrate having an active side containing a contact; forming a through silicon via extending through the wafer substrate electrically connected to the contact having a via width; forming a first coupling feature extending from a top side of the through silicon via; and forming a second coupling feature on the side of the through silicon via opposite the first coupling feature.