TSV Current Distribution in 3D Semiconductor Stacks
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor devices with 3D chip stacks face challenges in providing adequate power and maintaining longevity due to uneven current distribution through through-substrate vias (TSVs), which can lead to premature failure when current exceeds a threshold.
Innovation Solution
The method involves forming conductive lines associated with TSVs closer to the current source with narrower widths than those further away, varying the width and length of conductive lines to distribute current more evenly across TSVs, and strategically disconnecting interconnection contacts to maintain current below a threshold, thereby extending the operational lifetime of TSVs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conductive lines are made narrower to reduce current, then current threshold is maintained, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the current distribution problem by treating each TSV and its associated conductive line as an independent controllable unit. By calculating and setting specific width and length values for each conductive line individually, the system achieves precise current control through segmented optimization rather than uniform design
Solution Approach 2:
The patent performs preliminary calculation and design of conductive line dimensions before manufacturing. The width and length of each conductive line are predetermined based on its distance from the current source and desired current flow, allowing manufacturing to follow a pre-planned specification rather than requiring post-manufacturing adjustment
Data Source
Figure 1~2
Figure 3
Figure 4
AI summary
Semiconductor devices having modified current distribution and methods of forming the same are described herein. As an example, a memory die in contact with a logic die can be configured to draw a sum amount of current from a current source. The memory die can include a plurality of through-substrate vias (TSVs) formed in the memory die and configured to provide the sum amount of current to the memory die from the current source. The memory die can include at least two interconnection contacts associated with a first TSV closer to the current source that are not connected. The memory die can include an electrical connection between at least two interconnection contacts associated with a second TSV that is further in distance from the current source than the first TSV.