Decoupling Capacitor Chip Stacked via TSV for Noise Reduction
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Solution Overview
Problem
Conventional semiconductor devices face challenges in efficiently removing power ground grid noise due to limited space for decoupling capacitors, which increases with higher operation speeds, requiring multiple capacitors and complex fabrication processes.
Innovation Solution
A semiconductor device and package design where a decoupling capacitor is formed on a separate chip, allowing for increased capacitance without area expansion, using a Through Silicon Via (TSV) process for connection, enabling efficient noise removal without space limitations and simplifying fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple decoupling capacitors are arranged on the same chip to minimize power ground grid noise, then the noise removal capability is improved, but the chip area increases
Solution Approach 1:
The patent divides the semiconductor device into multiple chips: a first chip containing the decoupling capacitor and a second chip containing the internal circuits. This segmentation allows the decoupling capacitor to be placed on a separate chip, eliminating the area constraint on the original chip while maintaining noise removal functionality.
Solution Approach 2:
The patent transitions from a two-dimensional planar arrangement of capacitors on a single chip to a three-dimensional stacked configuration using Through Silicon Vias (TSVs). The decoupling capacitor is placed on a separate chip that is vertically connected to the main chip, utilizing the vertical dimension to resolve the area conflict.
2Reliability
If more decoupling capacitors are deployed to handle increased power ground grid noise from higher operation speeds, then the noise removal capability is improved, but the space for deploying capacitors is limited
Solution Approach 1:
By segmenting the device into multiple chips with the decoupling capacitor on a separate first chip and internal circuits on a second chip, the patent eliminates the space limitation problem. The first chip can be dedicated entirely to housing decoupling capacitors without competing for space with circuit components.
Solution Approach 2:
The patent uses vertical stacking through TSVs to move the decoupling capacitor to another dimension (vertical layer), effectively infiniteing the available space for capacitors by allowing multiple capacitor layers or larger capacitor structures on the separate first chip.
3Reliability
If multiple decoupling capacitors are arranged to ensure enough capacitance, then the noise removal capability is improved, but the fabrication process becomes more complex
Solution Approach 1:
The patent simplifies fabrication by segregating the decoupling capacitor fabrication on the first chip from the internal circuit fabrication on the second chip. This allows each chip to be optimized and fabricated independently using standard processes, then connected through TSVs, reducing overall fabrication complexity compared to integrating multiple capacitors and circuits on a single chip.
Data Source
AI summary
Provided is a semiconductor device capable of removing a power ground grid noise using a small area. The semiconductor device includes a first chip including at least one decoupling capacitor; and a second semiconductor chip stacked over the first semiconductor chip, including internal circuits.